rtl-synthesis

Star

Here are 7 public repositories matching this topic...

aryan-yadav4149 / 4Bit-Alu-Yosys-Symthesis

Star

4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground

mapping system-verilog yosys digital-design vlsi-design open-source-eda rtl-synthesis abc-tech eda-playground 4bit-alu

Updated Jun 5, 2026
SystemVerilog

Harsh-patil28 / DFT_Design_for_Testibility

Star

This repository documents the Design for Test (DFT) Flow that I am currently exploring during my internship.

rtl tcl-scripts rtl-synthesis scan-insertion

Updated Jul 31, 2025
Stata

ubyhzargam / Verilog_codes_synthesised_using_yosys

Star

These are verilog codes that are synthesized using open source tool yosys. We can do technology mapping using netlist, we can also estimate the area of design using info given in library.

rtl verilog synthesis logic-synthesis yosys digital-circuits technology-mapping rtl-synthesis

Updated Dec 4, 2024

Sudeep-Dhurua / verilog-to-gate-level-synthesis

Star

This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.

verilog-hdl vlsi-cad rtl-synthesis

Updated Apr 11, 2021

Brafamous / 8_bit_CPU_RTL_Synthesis

Star

8-bit CPU RTL synthesis flow using Verilog, Yosys, SKY130 standard cells, OpenSTA timing analysis, and ASIC-readiness documentation.

asic rtl verilog vlsi yosys digital-design cpu-design opensta openlane sky130 rtl-synthesis

Updated Jun 26, 2026
Verilog

kshitijnarendrakumar / IIR_Filter

Star

Direct Form-I IIR biquad in Verilog, synthesized with Cadence Genus. My contribution: functional simulation and synthesis-report analysis.

dsp verilog iir-filters digital-filters asic-design rtl-synthesis cadence-genus

Updated Aug 2, 2026
Verilog

KARAN-D05 / Harvard-Processor

Star

A parameterized multi-cycle Harvard architecture processor designed from the ground up in Verilog. Developed using a complete RTL design workflow including simulation, linting, synthesis, Sky130 technology mapping, area estimation, static timing analysis, cocotb self-checking testbenches and post synthesis GLS 🖥️.

computer-architecture instruction-set-architecture microarchitecture computer-organization performance-modeling turing-complete static-timing-analysis harvard-architecture computer-design rtl-synthesis amdahls-law self-checking-testbenches

Updated Aug 7, 2026
Verilog

Improve this page

Add a description, image, and links to the rtl-synthesis topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the rtl-synthesis topic, visit your repo's landing page and select "manage topics."

Learn more