This repository documents the Design for Test (DFT) Flow that I am currently exploring during my internship.
- Cadence Genus installed and licensed
- Cadence Tempus installed and licensed
- Mentor Grpahics Tessent installed and licensed
- Valid library files (.lib, .lef, .mdt) in project directories
- UNIX/Linux environment
🔹 Cadence Genus (Synthesis) – Logic synthesis and netlist generation.
🔹 Siemens Tessent (DFT) – Scan chain insertion, ATPG pattern generation, and Memory Built in Self Test.
🔹 Cadence Tempus (Static Timing Analysis) – Timing verification and analysis.
For any queries or contributions, feel free to open an issue or submit a pull request! 🚀
For issues contact:
Harsh A Patil
harshpatilhp28@gmail.com