cadence-genus

Here are 6 public repositories matching this topic...

Ad1thh / Final-Project-EV

Synthesizable 3-stage pipelined RV32E RISC-V processor core in SystemVerilog-2012 for Artix-7 FPGA (Nexys 4) and ASIC. Features hazard forwarding, 32KB BRAM, MMIO LED peripherals, 100% RISC-V ACT 4.0 compliance (195/195 tests passed), live silicon validation, and ongoing ECC SEC-DED fault-tolerance & Cadence Genus ASIC synthesis extensions.

fpga fault-tolerance systemverilog fault-injection risc-v xilinx-vivado tmr compliance-testing rv32e asic-design nexys4-board cadence-innovus cadence-xcelium cadence-genus sec-ded

Updated Aug 23, 2026
SystemVerilog

PreethamSK163 / Publication-3-Adaptive-Quadrant-Multiplier-SCI-Journal

Star

Adaptive Quadrant (AQ) reconfigurable 16-bit multiplier using quadrant decomposition and row bypassing for low-power operation. Implemented in RCA and hybrid prefix adder variants across TSMC 180nm/90nm using Cadence tools. Achieves significant power and area reduction with scalable architecture. SCI journal manuscript under review.

verilog-hdl power-analysis static-timing-analysis physical-design rtl-design cadence-innovus cadence-genus tsmc-180nm tsmc-90nm parallel-prefix-adders

Updated Apr 3, 2026

kshitijnarendrakumar / IIR_Filter

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Direct Form-I IIR biquad in Verilog, synthesized with Cadence Genus. My contribution: functional simulation and synthesis-report analysis.

dsp verilog iir-filters digital-filters asic-design rtl-synthesis cadence-genus

Updated Aug 2, 2026
Verilog

Varun2459 / Approximate-Multiplier-90nm-CMOS

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ASIC synthesis of approximate constant-carry multipliers at 90 nm CMOS. Cadence Genus/Tempus, QuestaSim, MATLAB PSNR/SSIM validation. 96.9% power reduction, 95.5% area reduction vs standard array multiplier.

asic dsp verilog vlsi questasim low-power approximate-computing cadence-genus

Updated Jun 7, 2026
Verilog

PreethamSK163 / Publication-2-Softmax-Processing-Unit-Patent

Star

Low-power fixed-point Softmax processing unit with LUT-based exponentiation and an 8-stage pipelined Mitchell logarithmic divider. Designed in Verilog and implemented on TSMC 180nm using Cadence tools. Achieves 1 output/cycle throughput and 8.9× speedup over sequential division. Patent under review.

verilog-hdl fixed-point-arithmetic cadence-innovus pipeline-design fsm-design cadence-genus tsmc-180nm dnn-hardware-accelerators

Updated Apr 2, 2026

PreethamSK163 / Publication-1-Dynamic-Reconfigurable-Binary-Multiplier-Patent

Star

Dynamic reconfigurable binary multiplier using quadrant decomposition and adaptive row bypassing for scalable, low-power operation. Designed in Verilog and implemented on TSMC 180nm/90nm using Cadence tools. Published Indian patent (202541080342).

verilog-hdl cadence-innovus rtl-to-gdsii cadence-genus tsmc-180nm tsmc-90nm low-power-vlsi digital-arithmetic-circuits

Updated Apr 2, 2026

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