Two-stage Miller-compensated CMOS OTA design and simulation using TSMC 180nm PDK and LTSpice.
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Jun 7, 2026
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tsmc-180nm
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Dynamic reconfigurable binary multiplier using quadrant decomposition and adaptive row bypassing for scalable, low-power operation. Designed in Verilog and implemented on TSMC 180nm/90nm using Cadence tools. Published Indian patent (202541080342).
verilog-hdl cadence-innovus rtl-to-gdsii cadence-genus tsmc-180nm tsmc-90nm low-power-vlsi digital-arithmetic-circuits
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Apr 2, 2026
Adaptive Quadrant (AQ) reconfigurable 16-bit multiplier using quadrant decomposition and row bypassing for low-power operation. Implemented in RCA and hybrid prefix adder variants across TSMC 180nm/90nm using Cadence tools. Achieves significant power and area reduction with scalable architecture. SCI journal manuscript under review.
verilog-hdl power-analysis static-timing-analysis physical-design rtl-design cadence-innovus cadence-genus tsmc-180nm tsmc-90nm parallel-prefix-adders
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Apr 3, 2026
Low-power fixed-point Softmax processing unit with LUT-based exponentiation and an 8-stage pipelined Mitchell logarithmic divider. Designed in Verilog and implemented on TSMC 180nm using Cadence tools. Achieves 1 output/cycle throughput and 8.9× speedup over sequential division. Patent under review.
verilog-hdl fixed-point-arithmetic cadence-innovus pipeline-design fsm-design cadence-genus tsmc-180nm dnn-hardware-accelerators
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Apr 2, 2026
Design and ADS simulation of a 1.8 V two-stage 180 nm CMOS op-amp, including compensation trade-offs, closed-loop stability, and a separate noise study.
cmos analog-design stability-analysis noise-analysis operational-amplifier keysight-ads tsmc-180nm frequency-compensation
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Aug 14, 2026 - TeX
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