Place single rail-only decoupling capacitors beside their chips

[mohan-bee]

Motivation

A single rail-only decoupling capacitor was identified as belonging to a chip and assigned to the correct side, but it was left as an ordinary standalone partition. Without a strongly connected component on that side, the later placement pass also had no alignment anchor. In the power-section reproduction this left C1 far above and to the right of U3 instead of beside U3's left edge.

Change

• Create decoupling partitions for rail-only singleton capacitors while keeping strongly connected singletons in their main partition.
• Fall back to the main chip as the row alignment anchor when its side has no strongly connected neighbor.
• Require 2 × chipGap for decoupling rows; reject the side move instead of placing them closer when that clearance collides.
• Add numeric assertions that C1 remains at least 2 × chipGap from U3 without overlaps.
• Refresh the affected schematic snapshots for the power-section, ADXL345, and RP2040 power-supply reproductions.

Evidence

The existing repro-power-section input exercises the missing case: C1 shares U3's positive and ground rails but has no direct pin-to-pin connection. The regression now checks the resulting geometry numerically in addition to the SVG snapshot.

Tests

• bun test — 81 passed, 1 skipped, 0 failed
• bun run format:check
• bun run build

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Project	Deployment	Actions	Updated (UTC)
matchpack	Ready	Preview	Jul 31, 2026 5:24pm

[mohan-bee]

refrence