Add per-register port handlers - #182
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Allow callers to select native, low-high, or high-low access for xHCI 64-bit MMIO registers. Keep native access as the default for existing users while making split access available for platforms and controllers that cannot accept native 64-bit MMIO operations.
The USB legacy support control/status register is the second dword of the capability. Map it at base + 4 instead of aliasing the legacy support semaphore register.
The Doorbell Array contains entry zero for the host controller followed by one entry for each device slot. Include that first entry in the accessor length so the highest valid slot ID remains addressable.
Read-modify-write users need to explicitly write zero to unrelated W1S bits. Add set_0 accessors matching the existing RW1C API so updating one field cannot accidentally trigger another write-one action.
Avoid reading and writing an entire Port Register Set when modifying one register. Provide read-only and mutable port handlers with an accessor for each register, matching the existing interrupter API.
This was referenced Aug 5, 2026
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This PR is part of a stack of 5 bookmarks:
Created with jj-stack |
This was referenced Aug 5, 2026
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Superseded by the stacked PR: ArthurHeymans#5. |
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Updating one port register through the whole
PortRegisterSetreads and writes the other three registers as well. That is unsafe for registers with write-one actions and can also touch reserved fields.Replace the array-wide accessor used by
Registerswith per-port handlers that map each register separately. Read-only access stays read-only, while mutable handlers retain exclusive access through the parent array.