Skip to content
View umeshkannakb's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report umeshkannakb

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. umeshkannakb umeshkannakb Public

    GitHub Profile README for Umesh Kanna K B

    1

  2. RTL-to-GDSII-Booth-Multiplier RTL-to-GDSII-Booth-Multiplier Public

    RTL to GDSII of Radix-4 Booth Multiplier using Cadence Genus and Innovus - full ASIC design flow

    Verilog

  3. NPTEL-CERTIFICATIONS NPTEL-CERTIFICATIONS Public

    NPTEL certifications across VLSI, Computer Architecture, Programming, Mathematics and emerging tech

  4. Certificates Certificates Public

    Course certifications, internship completion certificates and language proficiency achievements

  5. my-codeworks-HDLBits my-codeworks-HDLBits Public

    Personal solutions to HDLBits digital logic exercises - combinational, sequential, FSM and arithmetic in Verilog

  6. MIPS32-SINGLE-CYCLE-CPU-FOR-FPGA MIPS32-SINGLE-CYCLE-CPU-FOR-FPGA Public

    32-bit single-cycle MIPS processor in Verilog HDL, synthesizable on Xilinx FPGA

    Verilog