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add riscv64 CPU compatibility#257

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Xeonacid:fix-riscv64-cpu-compat
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add riscv64 CPU compatibility#257
Xeonacid wants to merge 1 commit into
tzcnt:mainfrom
Xeonacid:fix-riscv64-cpu-compat

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@Xeonacid

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Add a riscv64 branch that uses the Zihintpause pause instruction when the target enables it, otherwise falls back to a nop that is valid for the baseline ISA.

Read the Linux device-tree timebase-frequency value from procfs or sysfs as the counter frequency, and use rdtime for timestamps so both helpers use the RISC-V time counter units.

Add a riscv64 branch that uses the Zihintpause pause instruction when the target enables it, otherwise falls back to a nop that is valid for the baseline ISA. Read the Linux device-tree timebase-frequency value from procfs or sysfs as the counter frequency, and use rdtime for timestamps so both helpers use the RISC-V time counter units.
}
}
}
__builtin_unreachable();

@tzcnt tzcnt Jun 20, 2026

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Please add a fallback return value if this is not available. This value is used for heuristics only as described on line 78, so please choose a reasonable value for a RISC-V chip that supports multi-core / multi-thread.

@tzcnt tzcnt Jun 20, 2026

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Additionally, I think this needs an #ifdef __linux__ check. If not defined, we should also return a fallback.

#include <atomic>
#include <cstddef>
#include <cstdint>
#include <cstdio>

@tzcnt tzcnt Jun 20, 2026

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Please move this include inside of the #if defined(__riscv) block. This header is included almost everywhere in the project, so I try to keep it as slim as possible.

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