vedic-multiplier

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oluwaferanmi-arowoshola / vedic-multiplier-vlsi-design

Full-custom 8-bit pipelined Vedic multiplier in 90nm CMOS with hierarchical schematic/layout design, DRC/LVS-clean verification, post-layout simulation, and 50 MHz pipelined operation.

spice computer-architecture vlsi semiconductor cmos digital-design lvs drc circuit-design timing-analysis synopsys-custom-compiler layout-design physical-verification full-custom-layout vedic-multiplier pipelined-architecture

Updated May 16, 2026

Sanjayks683 / Advanced-32-bit-and-64-bit-Vedic-Multipliers-using-CSLA

Star

High-speed 32-bit and 64-bit Urdhva Tiryagbhyam Vedic multipliers using Carry Select Adders (CSLA) in Verilog.

verilog digital-design vedic-multiplier

Updated Jun 10, 2026
Verilog

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