This project presents a scalable, high-performance VLSI router architecture for Network-on-Chip (NoC) platforms, using Code Division Multiple Access (CDMA) to enable concurrent data transfers with reduced latency and power consumption. Built with Verilog HDL and implemented on an Artix-7 FPGA.

In this repo, I have designed a 4-2 compressor and 3-2 compressor based 8x8 dadda multiplier

RTL design and functional verification of a 32-bit ALU using Verilog HDL. Supports arithmetic, logical, and shift operations with corner-case handling such as divide-by-zero, underflow, and tri-state output enable. Simulated and verified using Xilinx ISE.

This repository contains the report of the Week 3 task for VSD RV SoC Tapeout Program

Hands-on FPGA and RTL design projects, including synthesis, simulation, and implementation using Verilog/VHDL in the Xilinx Vivado 2024.1, with ongoing self-learning and actively developing skills using the Cmod A7 FPGA Board (Xilinx Artix-7 35T).

A collection of 5 RTL digital design modules implemented in Verilog and simulated using ModelSim — covering UART, FIFO, Traffic Light Controller, Automatic Temperature Control, and Washing Machine Controller, each designed using FSM-based architecture with draw.io block diagrams, state transition tables, and waveform verification.

🔍 Conduct an in-depth review of Week 3 tasks for the VSD RV SoC Tapeout Program, showcasing key findings and insights.