✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
-
Updated
Feb 22, 2026 - Python
#
riscof
Here are 4 public repositories matching this topic...
A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.
processor-architecture fpga processor riscv rtl vivado systemverilog hdl risc-v rv32i verilator processor-design fpga-programming arty-a7 risc-v-architecture five-stage riscof pipelined-processor rv32i-processor
-
Updated
Jul 27, 2025 - SystemVerilog
A 5-stage pipelined RV32I core in SystemVerilog. Full forwarding, load-use stalling, early branch resolution. RISCOF-verified against Spike, synthesized on a Zynq-7000.
cpu fpga verilog xilinx vivado systemverilog computer-architecture risc-v rv32i pynq-z2 riscof pipelined-processor
-
Updated
Jun 10, 2026 - SystemVerilog
Add this topic to your repo
To associate your repository with the riscof topic, visit your repo's landing page and select "manage topics."