register-file

Hardware designs modelled with verilog

This is an implementation of a simple CPU in Logisim and Verilog.

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.

Computer Architecture - Practical Solution with Quartus - Sharif University of Technology

Processor VHDL 💾 assignments for module: CSU22022

VHDL register file with generic bitwidth, number of global register, number of windows, and number of registers per window.

A simple RISC processor designed in Verilog HDL, demonstrating fundamental CPU architecture concepts such as instruction execution, ALU operations, register files, memory access, and control logic.

Parameterized 8x16 register file in Verilog with read/write control, reset behavior, and testbench verification.

8-bit custom MCU built in Logisim Evolution that executes cyclic array rotation using a handcrafted ISA, register file, ALU, control unit, and data memory — fully functional single-cycle processor.

Logisim implementation of a custom 22-bit MIPS-like single-cycle datapath with control unit and a Python assembler that outputs Logisim ROM images.

Implementação didática de um processador de 16 bits multiciclo em Logisim, com arquitetura Harvard, 16 registradores, ULA, unidade de controle e memórias separadas para programa e dados.

4-Bit Register File Designs. This repository features two designs: a minimalist RB1574B using 74HC157 multiplexers for selective reads, and a full RB1534B using 74HC153 multiplexers for complete read/write flexibility. Includes technical details, IC lists and wiring strategies.

Standalone 16-bit ALU + 8x16 register-file datapath in SystemVerilog, with self-checking testbench and Icarus/GTKWave simulation.

Verilog implementation of a simple 16-bit CPU with datapath, ALU, register files and instruction execution.

Проектирование микропроцессора по микроархитектуре RISC-V на SystemVerilog + ASM

This is a 16-bit R-type instruction processor with register file, UAL, and instruction memory (RAM). Ideal for learning about processor design, it supports 8 arithmetic and logic operations and provides a starting point for building more complex designs.

VHDL project for implementing register files and sequential circuits, with testbench-based verification using ModelSim (Digital Circuit Design, UNIWA).

SystemVerilog DV of a RISC-V register file with fault injection and coverage analysis

16 bit processor designed in logisim