A C++ simulator for a 32-bit split-L1 cache (separate I/D) with MESI coherence, pseudo-LRU replacement, and write-back/write-allocate policy — reads a trace and reports hit/miss statistics or per-operation L2 bus messages.
cpp cpu-cache computer-architecture cache-simulator memory-hierarchy mesi cache-coherence write-back pseudo-lru
-
Updated
Jul 4, 2026 - C++