Project assigment submission for the course "Prova Finale (progetto di reti logiche)" @ Polimi A.A. 23/24
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Updated
Oct 6, 2025 - TeX
Project assigment submission for the course "Prova Finale (progetto di reti logiche)" @ Polimi A.A. 23/24
Síntesis de multiplicadores binarios mediante RL tabular: agentes Monte Carlo, Q-learning y SARSA rellenan tablas de productos parciales verificadas en Verilog (Icarus, CPU) o evaluadas como tensores batched en GPU (PyTorch/CUDA).
Verified Boolean-circuit research releases and reproducible search methods
Verified 29-AND AES S-box circuits: 158 XOR/depth 30 and 159 XOR/depth 29
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