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Rakesh-2306 / Design-and-analysis-of-Low-power-hybrid-full-adder-for-array-multiplier-in-90nm-technology

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Designed and implemented a low-power hybrid full adder and 4-bit/8-bit array multipliers in GPDK 90nm CMOS using Cadence Virtuoso, including schematic design, full-custom layout, DRC/LVS verification, PEX, and post-layout performance analysis.

cadence-virtuoso low-power full-adder low-power-comsumption assura array-multiplier post-layout-simulation design-rule-check low-power-design transmission-gate-logic full-custom-layout layout-vs-schematic gpdk90nm
  • Updated Oct 21, 2025

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