Popular repositories Loading

1. asic-flow-automation asic-flow-automation Public

   Automated Physical Design Flow Manager using Python.

   Python 2 1

2. 3des-verilog-hdl-implementation 3des-verilog-hdl-implementation Public

   A complete, synthesizable standard Triple DES (3DES) EDE mode encryption/decryption IP core implemented in Verilog HDL.

   Verilog 2

3. fpga-median-filter-soc-de2 fpga-median-filter-soc-de2 Public

   Hardware-accelerated 3×3 median filter SoC on Altera DE2 (Cyclone II) using Nios II CPU, Avalon-MM bus, and a pipelined sorting-network IP core — implemented in Verilog with Quartus II 13.0 SP1.

   Verilog 1