Search results

[P0] Conv test numerical value mismatch

Status: Open.

#292 In tancheng/VectorCGRA;

· guosran opened on May 28, 2026

[P3] Width Mismatch for Heterogeneous Submodule Interface Arrays in the stage of PyMTL Verilog Translation

Status: Open.

#289 In tancheng/VectorCGRA;

· BenkangPeng opened on May 8, 2026

[P0] Overwrite and overuse the same register in xbar

bugSomething isn't workingSomething isn't working

Status: Open.

#286 In tancheng/VectorCGRA;

· tancheng opened on Apr 23, 2026

Needed Packages for Simple Addition

Status: Open.

#284 In tancheng/VectorCGRA;

· Lee404notfound opened on Apr 15, 2026

[P0] Simulator and rtl comparison (latency gap) debug

Status: Open.

#281 In tancheng/VectorCGRA;

· n0thingNoob opened on Apr 8, 2026

[P1] Support for GEP Operand

new featureNew feature or requestNew feature or request

Status: Open.

#279 In tancheng/VectorCGRA;

· Jackcuii opened on Mar 29, 2026

[P1] Heterogeneous Multi-CGRA

Status: Open.

#277 In tancheng/VectorCGRA;

· tancheng opened on Mar 26, 2026

[P1] Write value into register from const_queue not implemented

Status: Open.

#268 In tancheng/VectorCGRA;

· Jackcuii opened on Mar 4, 2026

[P3] MemUnit is not fusible

bugSomething isn't workingSomething isn't working

Status: Open.

#214 In tancheng/VectorCGRA;

· tancheng opened on Nov 1, 2025

Questions on Bridging to VectorCGRA

questionFurther information is requestedFurther information is requested

Status: Open.

#195 In tancheng/VectorCGRA;

· n0thingNoob opened on Oct 14, 2025

[P1] Support allocate operations in FU

Status: Open.

#193 In tancheng/VectorCGRA;

· ShangkunLi opened on Sep 30, 2025

[P0] Another simple test (hand-written)

test

Status: Open.

#189 In tancheng/VectorCGRA;

· tancheng opened on Sep 13, 2025