arm_v81m: model Cortex-M55 shifted operand latency

[bremoran]

Fixes #463

Summary

Model the additional Cortex-M55 latency when a producer feeds the flexible
shifted-register Operand2 (Rm) of scalar instructions.

The model now covers all flexible Operand2 instruction families documented in
the Cortex-M55 Software Optimization Guide:

• ADC
• ADD
• AND
• BIC
• CMN
• CMP
• EOR
• MVN
• ORN
• ORR
• RSB
• SBC
• SUB
• TEQ
• TST

The latency remains unchanged when the producer feeds the unshifted operand.
PKHBT/PKHTB remain separate because they are fixed-latency packing
instructions, not flexible Operand2 forms.

A shared ShiftedOperandInstruction base class provides consistent parsing and
operand identification. The M55 and M85 target models use operand-aware
dependency matching, including multi-output and input/output producers.
Carry-flag and comparison/test flag semantics are covered explicitly.

Motivation

The previous implementation modeled only ADD, EOR, ORR, AND, and BIC because
those were sufficient for the Keccak scheduling workload. The instruction-set
reference defines the shifted Operand2 form more broadly, so the model should
represent the full instruction family rather than a workload-specific subset.

Performance evidence

The historical Keccak measurements motivating this change remain:

Schedule	Cycles	Delta vs M7
M7 schedule	9851	—
M55 schedule with shifted-source latency	9502	-349

The Keccak input uses only the already-supported EOR and BIC shifted forms, so
the generalized model produces the same Keccak dependency latencies as the
previous implementation. New hardware measurements are not included in this
model-expansion PR.

Testing

• Armv8-M instruction-model and memory-model tests
• M55 and M85 target test suites with -W error
• M55 and M85 example dry-runs
• flake8 .
• black --check --diff .
• git diff --check