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KTH Silago Team

10 followers
Sweden
https://silago.eecs.kth.se

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README.md

Welcome to the SiLago project

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vesyla vesyla Public

Tool suite for DRRA hardware accelerator platform

C++ 3 1

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All C C++ HTML JavaScript MLIR Rust SCSS Shell SystemVerilog Tcl VHDL

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Showing 10 of 23 repositories

drra-components Public
DRRA Component Library

silagokth/drra-components's past year of commit activity

C++ 2 GPL-3.0 0 5 (1 issue needs help) 7 Updated Aug 27, 2026
vesyla Public
Tool suite for DRRA hardware accelerator platform

silagokth/vesyla's past year of commit activity

C++ 3 GPL-3.0 1 9 (1 issue needs help) 5 Updated Aug 26, 2026
il2234-lab-demo Public

silagokth/il2234-lab-demo's past year of commit activity

Tcl 2 1 0 0 Updated Aug 18, 2026
SiLagoDoc Public
Documentation of SiLago platform

silagokth/SiLagoDoc's past year of commit activity

6 1 0 0 Updated Jun 23, 2026
sylva-suite Public
ALS for Silago

silagokth/sylva-suite's past year of commit activity

Rust 0 GPL-3.0 0 6 0 Updated Jun 23, 2026
sylva-components Public
Sylva RTL components to compose the full system at RTL level

silagokth/sylva-components's past year of commit activity

SystemVerilog 0 GPL-3.0 0 1 0 Updated Jun 17, 2026
ara Public Forked from pulp-platform/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

silagokth/ara's past year of commit activity

C 0 196 0 0 Updated Sep 26, 2025
Stream-HLS Public Forked from UCLA-VAST/Stream-HLS
An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs

silagokth/Stream-HLS's past year of commit activity

MLIR 0 MIT 16 0 0 Updated Aug 1, 2025
memristor_MIMO Public
Experiments and simulation setup for MIMO in memory computation using memristors

silagokth/memristor_MIMO's past year of commit activity

VHDL 3 MIT 1 0 0 Updated Mar 14, 2025
drra2 Public archive
DRRA v2 project

silagokth/drra2's past year of commit activity

0 0 0 0 Updated Jan 16, 2025

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