Skip to content
View shrisha-katti's full-sized avatar
  • Bengaluru, India
  • Joined Aug 6, 2026

Block or report shrisha-katti

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
shrisha-katti/README.md

Hi there 👋

Popular repositories Loading

  1. shrisha-katti shrisha-katti Public

  2. riscv-asic-ppa-analysis riscv-asic-ppa-analysis Public

    Single-Cycle RISC-V Processor with AXI4-Lite Memory Subsystem in Verilog

    Verilog

  3. iscas89-dft-modus iscas89-dft-modus Public

    Design-for-Test (DFT) implementation and analysis using Cadence Modus on ISCAS'89 benchmark circuits.

    Verilog

  4. single-cycle-riscv-axi4lite single-cycle-riscv-axi4lite Public

    Single-cycle RISC-V processor with AXI4-Lite memory subsystem implemented in Verilog for FPGA synthesis and simulation.

    Verilog

  5. 8t-sram-array-cim 8t-sram-array-cim Public

    Design and simulation of an 8T SRAM array with Compute-in-Memory (MAC) functionality using Cadence Virtuoso in 90 nm CMOS.

  6. axi4-lite-layered-verification axi4-lite-layered-verification Public

    Layered SystemVerilog verification environment for validating an AXI4-Lite slave using constrained-random stimulus, assertions, and self-checking scoreboards.

    SystemVerilog