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Draft: Add new proprieties and wrappers functions#61

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tmarcero wants to merge 8 commits into
qualcomm:mainfrom
tmarcero:sail-platform
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Draft: Add new proprieties and wrappers functions#61
tmarcero wants to merge 8 commits into
qualcomm:mainfrom
tmarcero:sail-platform

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@tmarcero
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  • Update cortex-r52
  • arm_gicv3: Add first-cpu-index property
  • Add new wrappers functions
  • Add new power ON/OFF callback for ARM CPU
  • Add new write GPIO model
  • Add new wrapper function to set IMP_BUILDOPTR register
  • hexagon_qtimer: Add ticker_ctrl CCI param and make p_cnttid a vector

This PR follows this one:
qualcomm/qemu#142

@tmarcero tmarcero self-assigned this May 20, 2026
@tmarcero tmarcero changed the title SAIL Qbox Updates Draft: SAIL Qbox Updates May 20, 2026
@tmarcero tmarcero changed the title Draft: SAIL Qbox Updates Draft: Add new proprieties and wrappers functions May 20, 2026

switch (ret) {
case 0: // SUCCESS
break;
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seems a little excessive to do the, is there a 'perror' equivalent? Or should we just print the number, Also, is this ARM specific (as the error messages suggest)? this is in CPU.h so it should work for hexagon, riscv, ...?

tmarcero and others added 8 commits May 20, 2026 12:57
- libqemu-v11.0-v0.6: - qct-qtimer: add support for frame_stride property
- CortexR52: Add new pmsav8r_hdregion property
- Update set_cp15_cbar wrapper function
- Add new wrappers functions and export them with getter functions
- Add new wrapper function to set IMP_BUILDOPTR register
- qct-qtimer: add ticker-ctrl property and remove the start-ticking one (OnOffAuto)

Signed-off-by: Marceron Thomas <tmarcero@qti.qualcomm.com>
- Add EL2 property
- Add Multi-processor affinity property
- Add PMSAv7 and PMSAv8 properties to set the MPU number of supported regions
- Add CBAR property

Signed-off-by: tmarcero <tmarcero@quicinc.com>
- In the case of some SoC is using multiples GICs, we will need to
set this, otherwise we will have this kind of errors : `Assertion `oldreg->type & ARM_CP_OVERRIDE' failed`
which means that same GIC registers will be configured multiples times.
It's because the same CPU index will be return by `qemu_get_cpu` function except if we use this property.

Signed-off-by: tmarcero <tmarcero@quicinc.com>
- Add new getter functions to fetch QEMU properties
- Add ARM power control function to power on and unhalt CPUs

Signed-off-by: tmarcero <tmarcero@quicinc.com>
- Add new callback to power ON ARM cpus

Signed-off-by: tmarcero <tmarcero@quicinc.com>
- This model allows connecting multiple Target Signal Sockets using a multi Initiator socket.
It will set all targets connected to the multi initiator socket to '1' by default.
This allows defining GPIOs/fuses, for example.

Signed-off-by: tmarcero <tmarcero@quicinc.com>
- This register is specific to Cortex-R52, it need to be configured in some
specific chips which expect to have Bus protection bit set.

Signed-off-by: tmarcero <tmarcero@quicinc.com>
- p_cnttid is now a vector because some SoC can have more than 8 frames, so
we will have more than one CNTTID register.

- Add ticker_ctrl CCI param to handle if we want always running Qtimers or not.
ON: Qtimers will always tick
OFF: Qtimers will never tick
AUTO: Qtimers will be controlled entirely by SW

Signed-off-by: Marceron Thomas <tmarcero@qti.qualcomm.com>
bool value = m_int->exports().object_property_get_bool(m_obj, name, &e);

if (e != nullptr) {
throw GetPropertyException("bool", name, m_int->exports().error_get_pretty(e));
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I'm not sure throwing is a very good idea here, I think you should SC_REPORT_FATAL.....
Unless you really ARE try/catching these functions?

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where are the 'getters' used?

@tmarcero
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tmarcero commented May 20, 2026

where are the 'getters' used?

This is not used for the moment, it's in case of someone later want to use it, or for debug purpose :-)

@tmarcero tmarcero closed this May 20, 2026
@tmarcero tmarcero reopened this May 20, 2026
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