WORKAROUND: usb: host: xhci-pci-renesas: enable D3cold PME support#960
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akakum-qualcomm wants to merge 11 commits intoqualcomm-linux:mainfrom
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WORKAROUND: usb: host: xhci-pci-renesas: enable D3cold PME support#960akakum-qualcomm wants to merge 11 commits intoqualcomm-linux:mainfrom
akakum-qualcomm wants to merge 11 commits intoqualcomm-linux:mainfrom
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Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-6-46e085bca4cc@oss.qualcomm.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
Add support for SYSTEM_RESET2 vendor-specific resets in qcm6490-idp as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-8-46e085bca4cc@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
…ypes Add support for SYSTEM_RESET2 vendor-specific resets in qcs6490-rb3gen2 as reboot-modes. Describe the resets: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20251109-arm-psci-system_reset2-vendor-reboots-v17-9-46e085bca4cc@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Elliot Berman <elliot.berman@oss.qualcomm.com> Signed-off-by: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
Add a node for the TC9563 PCIe switch, which has three downstream ports. Two embedded Ethernet devices are present on one of the downstream ports. As all these ports are present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, controlled by two GPIOs, which are added as fixed regulators. Configure the TC9563 through I2C. Link: https://lore.kernel.org/r/20251101-tc9563-v9-7-de3429f7787a@oss.qualcomm.com Reviewed-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add reserved memory region for audio PD dynamic loading and remote heap requirement. Also add LPASS and ADSP_HEAP VMIDs. Link: https://lore.kernel.org/r/20251117070819.492-1-jianping.li@oss.qualcomm.com Signed-off-by: Jianping Li <jianping.li@oss.qualcomm.com>
…e configuration The QCS6490 rb3gen2 board uses the same Qualcomm QCM6490 platform but has a different thermal junction temperature specification due to package-level differences. Update passive/hot trip thresholds to 105°C and critical trip thresholds to 115°C for various subsystem TSENS sensors. Disable CPU cooling maps for CPU TSENS since CPU thermal mitigation is handled automatically in hardware on this board. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251215105934.2428987-1-manaf.pallikunhi@oss.qualcomm.com
Enable cdsp cooling devices and cooling map bindings for cdsp. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251223123227.1317244-8-gaurav.kohli@oss.qualcomm.com
…2 industrial mezzanine
Below is the routing diagram of dsi lanes from qcs6490 soc to
mezzanine.
DSI0 --> SW1403.4 --> LT9611uxc --> hdmi port
|
--> SW2700.1 --> dsi connector
|
--> LT9211c --> LVDS connector
Disable hdmi connector for industrial mezzanine and enable
LT9211c bridge and lvds panel node.
LT9211c is powered by default with reset gpio connected to 117.
LVDS Disabled by default. we can enable it through weston.
Signed-off-by: Yi Zhang <zhanyi@qti.qualcomm.com>
Signed-off-by: Gopi Botlagunta <venkata.botlagunta@oss.qualcomm.com>
Link: https://lore.kernel.org/lkml/20251112-add-lt9211c-bridge-for-rb3gen2-industrial-mezzanine-v1-1-6eab844ec3ac@oss.qualcomm.com/
Add the PMU node for WCN6750 present on the qcm6490-idp board and assign its power outputs to the Bluetooth module. In WCN6750 module sw_ctrl and wifi-enable pins are handled in the wifi controller firmware. Therefore, it is not required to have those pins' entries in the PMU node. Link: https://lore.kernel.org/r/20260203071807.764036-1-janaki.thota@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Janaki Ramaiah Thota <janaki.thota@oss.qualcomm.com>
…icro-USB OTG Enable the secondary USB controller (USB2) and its High-Speed PHY to support OTG functionality via a Micro-USB connector. Define a dedicated 'usb2-connector' node using the 'gpio-usb-b-connector' compatible to handle ID and VBUS detection. Link this connector to the DWC3 controller via OF graph ports to satisfy schema requirements and enable role switching. Specific hardware configuration: - ID pin: TLMM 61 - VBUS detection: PM7325 GPIO 9 - VBUS supply: Fixed regulator controlled by TLMM 63 - Configure &usb_2 in OTG mode with role switching enabled. - Define a gpio-usb-b-connector node for Micro-USB support, mapping the ID pin to TLMM 61 and VBUS detection to PM7325 GPIO 9. - Add the 'vdd_micro_usb_vbus' fixed regulator (controlled by TLMM 63) to supply VBUS to the connector. - Add the 'usb2_id_detect' pinctrl state to configure GPIO 61 for ID detection. - Enable &usb_2_hsphy and populate necessary voltage supplies (VDDA PLL, VDDA 1.8V, VDDA 3.3V). Link: https://lore.kernel.org/all/c3on5e56hqipudpt7uyam2cples3rhadpz324zeg7nebczsglt@bxuy5jzrxjc7/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Set the PCI device PME support bit for D3cold in xhci_pci_renesas_probe(). Without advertising D3cold PME capability, the PCI PM core may avoid putting the Renesas xHCI controller into D3cold, preventing the PCIe device from reaching the deepest low-power state during suspend/runtime PM. Update dev->pme_support to include PCI_D3cold so the device is allowed to enter D3cold when appropriate. Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com> CRs-Fixed: 4495614
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Set the PCI device PME support bit for D3cold in
xhci_pci_renesas_probe().
Without advertising D3cold PME capability, the PCI PM core may avoid putting the Renesas xHCI controller into D3cold, preventing the PCIe device from reaching the deepest low-power state during suspend/runtime PM.
Update dev->pme_support to include PCI_D3cold so the device is allowed to enter D3cold when appropriate.
Signed-off-by: Akash Kumar akash.kumar@oss.qualcomm.com
CRs-Fixed: 4495614