refactor: migrate to common_cells v2

Bender.yml

@@ -22,8 +22,8 @@ package:
     - "Enrico Zelioli <ezelioli@iis.ee.ethz.ch>"
 
 dependencies:
-  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.26.0 }
-  register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.9 }
+  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 2.0.0-beta }
+  register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: common-cells-v2 }
 
 sources:
   - src/clic_pkg.sv

src/clic.sv

@@ -23,7 +23,7 @@ module clic
   import clicint_reg_pkg::*;
   import clicintv_reg_pkg::*;
   import clicvs_reg_pkg::*;
-  import cf_math_pkg::*;
+  import cc_pkg::*;
 #(
   parameter type reg_req_t = logic,
   parameter type reg_rsp_t = logic,
@@ -60,6 +60,7 @@ module clic
   output logic [7:0]        irq_level_o,
   output logic              irq_shv_o,
   output logic [1:0]        irq_priv_o,
+  output logic [1:0]        irq_rstk_o,
   output logic [VSID_W-1:0] irq_vsid_o,
   output logic              irq_v_o,
   output logic              irq_kill_req_o,
@@ -336,6 +337,8 @@ module clic
   logic [1:0] intmode [N_SOURCE];
   logic [1:0] irq_mode;
 
+  logic [1:0] intrstk [N_SOURCE];
+
   logic [VSID_W-1:0] vsid [N_SOURCE]; // Per-IRQ Virtual Supervisor (VS) ID
   logic              intv [N_SOURCE]; // Per-IRQ virtualization bit
 
@@ -383,6 +386,7 @@ module clic
 
     .prio_i      (intctl),
     .mode_i      (intmode),
+    .rstk_i      (intrstk),
     .intv_i      (intv),
     .vsid_i      (vsid),
 
@@ -395,6 +399,7 @@ module clic
     .irq_id_o,
     .irq_max_o   (irq_max),
     .irq_mode_o  (irq_mode),
+    .irq_rstk_o,
     .irq_v_o,
     .irq_vsid_o,
     .irq_shv_o,
@@ -714,6 +719,7 @@ module clic
 
     .intctl_o  (intctl),
     .intmode_o (intmode),
+    .intrstk_o (intrstk),
     .shv_o     (shv),
     .vsid_o    (vsid),
     .intv_o    (intv),

src/clic_reg_adapter.sv

@@ -20,7 +20,7 @@ module clic_reg_adapter
   import clicint_reg_pkg::*;
   import clicintv_reg_pkg::*;
   import clicvs_reg_pkg::*;
-  import cf_math_pkg::*;
+  import cc_pkg::*;
 #(
   parameter int N_SOURCE = 32,
   parameter int INTCTLBITS = 8,
@@ -41,6 +41,7 @@ module clic_reg_adapter
 
   output logic [7:0]              intctl_o  [N_SOURCE],
   output logic [1:0]              intmode_o [N_SOURCE],
+  output logic [1:0]              intrstk_o [N_SOURCE],
   output logic [VsidWidth-1:0]    vsid_o    [N_SOURCE], // interrupt VS id
   output logic                    intv_o    [N_SOURCE], // interrupt virtualization
   output logic [VsprioWidth-1:0]  vsprio_o  [MAX_VSCTXTS], // VS priority
@@ -60,6 +61,7 @@ module clic_reg_adapter
   for (genvar i = 0; i < N_SOURCE; i++) begin : gen_reghw
     assign intctl_o[i] = clicint_reg2hw[i].clicint.ctl.q;
     assign intmode_o[i] = clicint_reg2hw[i].clicint.attr_mode.q;
+    assign intrstk_o[i] = clicint_reg2hw[i].clicint.attr_rstk.q;
     assign shv_o[i] = clicint_reg2hw[i].clicint.attr_shv.q;
     assign ip_sw_o[i] = clicint_reg2hw[i].clicint.ip.q;
     assign ie_o[i] = clicint_reg2hw[i].clicint.ie.q;

src/clic_target.sv

@@ -50,6 +50,7 @@ module clic_target
 
   input [PrioWidth-1:0]        prio_i [N_SOURCE],
   input [ModeWidth-1:0]        mode_i [N_SOURCE],
+  input [          1:0]        rstk_i [N_SOURCE],
   input logic                  intv_i [N_SOURCE],
   input [VsidWidth-1:0]        vsid_i [N_SOURCE],
 
@@ -62,6 +63,7 @@ module clic_target
   output logic [SrcWidth-1:0]  irq_id_o,
   output logic [PrioWidth-1:0] irq_max_o,
   output logic [ModeWidth-1:0] irq_mode_o,
+  output logic [          1:0] irq_rstk_o,
   output logic [VsidWidth-1:0] irq_vsid_o,
   output logic                 irq_v_o,
   output logic                 irq_shv_o,
@@ -172,6 +174,7 @@ module clic_target
   prio_t                irq_max_d, irq_max_q;
   logic [VsidWidth-1:0] vsid_max_d, vsid_max_q;
   logic                 shv_max_d, shv_max_q;
+  logic [1:0]           rstk_max_d, rstk_max_q;
 
   // the results can be found at the tree root
   // TODO: remove useless inequality comparison
@@ -194,6 +197,7 @@ module clic_target
     irq_max_d = '0;
     vsid_max_d = '0;
     shv_max_d = '0;
+    rstk_max_d = '0;
     claim_o = '0;
 
     irq_valid_d = 1'b0;
@@ -209,6 +213,7 @@ module clic_target
           irq_max_d = max_tree[0];
           vsid_max_d = vsid_i[irq_root_id];
           shv_max_d = shv_i[irq_root_id];
+          rstk_max_d = rstk_i[irq_root_id];
           irq_valid_d = 1'b1;
           irq_state_d = ACK;
         end
@@ -219,6 +224,7 @@ module clic_target
         irq_max_d   = irq_max_q;
         vsid_max_d  = vsid_max_q;
         shv_max_d   = shv_max_q;
+        rstk_max_d  = rstk_max_q;
         // level sensitive interrupts (le_i == 1'b0) can be cleared (ip_i goes
         // to 1'b0) and shouldn't fire anymore so we should get unstuck here
         if (!le_i[irq_id_q] && !ip_i[irq_id_q]) begin
@@ -258,6 +264,7 @@ module clic_target
       irq_max_q <= '0;
       vsid_max_q <= '0;
       shv_max_q <= '0;
+      rstk_max_q <= '0;
       irq_kill_req_q <= 1'b0;
       irq_state_q <= IDLE;
     end else begin
@@ -266,6 +273,7 @@ module clic_target
       irq_max_q <= irq_max_d;
       vsid_max_q <= vsid_max_d;
       shv_max_q <= shv_max_d;
+      rstk_max_q <= rstk_max_d;
       irq_kill_req_q <= irq_kill_req_d;
       irq_state_q <= irq_state_d;
     end
@@ -280,6 +288,7 @@ module clic_target
   assign irq_vsid_o = vsid_max_q;
   assign irq_v_o    = logic'(irq_max_q.mode == S_MODE);
   assign irq_shv_o  = shv_max_q;
+  assign irq_rstk_o = rstk_max_q;
 
   assign irq_kill_req_o = irq_kill_req_q;
 

src/clicint_reg_pkg.sv

@@ -26,6 +26,9 @@ package clicint_reg_pkg;
     struct packed {
       logic [1:0]  q;
     } attr_trig;
+    struct packed {
+      logic [2:0]  q;
+    } attr_rstk;
     struct packed {
       logic [1:0]  q;
     } attr_mode;
@@ -43,7 +46,7 @@ package clicint_reg_pkg;
 
   // Register -> HW type
   typedef struct packed {
-    clicint_reg2hw_clicint_reg_t clicint; // [14:0]
+    clicint_reg2hw_clicint_reg_t clicint; // [17:0]
   } clicint_reg2hw_t;
 
   // HW -> register type

src/clicint_reg_top.sv

@@ -80,6 +80,9 @@ module clicint_reg_top #(
   logic [1:0] clicint_attr_trig_qs;
   logic [1:0] clicint_attr_trig_wd;
   logic clicint_attr_trig_we;
+  logic [2:0] clicint_attr_rstk_qs;
+  logic [2:0] clicint_attr_rstk_wd;
+  logic clicint_attr_rstk_we;
   logic [1:0] clicint_attr_mode_qs;
   logic [1:0] clicint_attr_mode_wd;
   logic clicint_attr_mode_we;
@@ -194,6 +197,32 @@ module clicint_reg_top #(
   );
 
 
+  //   F[attr_rstk]: 21:19
+  prim_subreg #(
+    .DW      (3),
+    .SWACCESS("RW"),
+    .RESVAL  (3'h0)
+  ) u_clicint_attr_rstk (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (clicint_attr_rstk_we),
+    .wd     (clicint_attr_rstk_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.clicint.attr_rstk.q ),
+
+    // to register interface (read)
+    .qs     (clicint_attr_rstk_qs)
+  );
+
+
   //   F[attr_mode]: 23:22
   prim_subreg #(
     .DW      (2),
@@ -274,6 +303,9 @@ module clicint_reg_top #(
   assign clicint_attr_trig_we = addr_hit[0] & reg_we & !reg_error;
   assign clicint_attr_trig_wd = reg_wdata[18:17];
 
+  assign clicint_attr_rstk_we = addr_hit[0] & reg_we & !reg_error;
+  assign clicint_attr_rstk_wd = reg_wdata[21:19];
+
   assign clicint_attr_mode_we = addr_hit[0] & reg_we & !reg_error;
   assign clicint_attr_mode_wd = reg_wdata[23:22];
 
@@ -289,6 +321,7 @@ module clicint_reg_top #(
         reg_rdata_next[8] = clicint_ie_qs;
         reg_rdata_next[16] = clicint_attr_shv_qs;
         reg_rdata_next[18:17] = clicint_attr_trig_qs;
+        reg_rdata_next[21:19] = clicint_attr_rstk_qs;
         reg_rdata_next[23:22] = clicint_attr_mode_qs;
         reg_rdata_next[31:24] = clicint_ctl_qs;
       end

src/gen/clicint.hjson

@@ -27,7 +27,7 @@
       fields: [
         { bits: "31:24", name: "CTL", desc: "interrupt control for interrupt" },
         { bits: "23:22", name: "ATTR_MODE", desc: "privilege mode of this interrupt", resval: 3},
-        //{ bits: "21:19", name: "reserved" },
+        { bits: "21:19", name: "ATTR_RSTK", desc: "determines which registers should be automatically pushed on stack", resval: 0 },
         { bits: "18:17", name: "ATTR_TRIG", desc: "specify trigger type for this interrupt" },
         { bits: "16", name: "ATTR_SHV", desc: "enable hardware vectoring for this interrupt" },