It takes an assembly file as input, parses the instructions and labels, and outputs a binary file containing the machine code.
Assembles a subset of RISC-V RV32I instructions, including:
- R-Type:
add, sub, sll, slt, sltu, xor, srl, sra, or, and - I-Type:
addi, slti, sltiu, xori, ori, andi, slli, srli, srai - S-Type:
sb, sh, sw - B-Type:
beq, bne, blt, bge, bltu, bgeu - U-Type:
lui, auipc - J-Type:
jal
Supports labels for branches and jumps, automatically calculating offsets.
Handles both ABI names (e.g., ra, sp, t0) and numerical x registers (e.g., x1, x2).
Generates a .bin file containing the assembled machine code.
Rust: Ensure you have Rust and Cargo installed. If not, you can install it from rust-lang.org.
Clone the repository:
git clone https://github.com/pranav-avn/riscAs
cd riscAsBuild the project:
cargo build --releaseThis will create an executable in the target/release/ directory.
To assemble an assembly file, run the compiled executable with the input assembly file and the desired output file name:
./target/release/riscAs <input_assembly_file.asm> <output_binary_file_name>Let's say you have an assembly file named example.asm:
# test risc-v assembly file
.main:
addi t0, zero, 1 # initialize t0 to 1
addi s0, zero, 0 # result (s0) = 0
addi t1, zero, 10 # loop end value
.loop:
add s0, s0, t0 # add to the result
addi t0, t0, 1 # increment the counter
bge t1, t0, .loop # loop conditionTo assemble it into program.bin, you would run:
./target/release/riscAs example.asm programThis will generate a file named program.bin in the current directory.
The entry point of the assembler, handling file I/O and orchestrating the parsing process.
Contains the core logic for parsing assembly instructions, encoding them into machine code, and resolving labels.