Watchdog for ZynqMP RPU by kber-ps · Pull Request #789 · phoenix-rtos/phoenix-rtos-kernel

kber-ps · 2026-06-15T12:54:14Z

Description

This PR introduces Watchdog handlers for ZynqMP RPU

LPD (low power domain) SWDT (Software watchdog)
LPD bus clock with 512 scaler used for watchdog counter
hal_wdgReload is now defined
platformctl: pctl_wdg_reload and pctl_wdg_enable (set new reload value,
enable/disable respectively) are now defined

Motivation and Context

The ZynqMP RPU targets critical application in UAV domain. By default it is configured
to run in lock-step. Watchdog support is required for this kind of application.s

Types of changes

Bug fix (non-breaking change which fixes an issue)
New feature (non-breaking change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to change)
Chore (refactoring, style fixes, git/CI config, submodule management, no code logic changes)

How Has This Been Tested?

Already covered by automatic testing.
New test added: (add PR link here).
Tested by hand on: (list targets here).

Checklist:

My change requires a change to the documentation.
I have updated the documentation accordingly.
I have added tests to cover my changes.
All new and existing linter checks and tests passed.
My changes generate no new compilation warnings for any of the targets.

Special treatment

This PR needs additional PRs to work (list the PRs, preferably in merge-order).
I will merge this PR by myself when appropriate.

- kernel level watchdog initialization - reload value in board_config.h for user - watchdog prescaler set to 512 (LPD_LSBUS_CLK) - RPU reset on timeout - syscall for reload YT: DO-836

github-actions · 2026-06-15T12:54:35Z

+	*(zynq_common.swdt_lpd + swdt_lpd_control) = (SWDT_CONTROL_CKEY | (0xFFF << SWDT_CONTROL_CRV_BIT)| SWDT_CONTROL_CLKSEL );
+
+#if defined(WATCHDOG)
+	/* set cotnrol: LPD_LSBUS_CLK scaler = 512 (gives reload value from ~20ms to 85s fro 100MHz LPD_LSBUS_CLK)*/


[codespell] _{reported by reviewdog 🐶}
fro ==> for, from

github-actions · 2026-06-15T12:54:37Z

+	 * in the UG: "Note: If a restart signal is received the prescaler should be reset."
+	 */
+	*(zynq_common.swdt_lpd + swdt_lpd_mode) = (SWDT_MODE_ZKEY);
+	*(zynq_common.swdt_lpd + swdt_lpd_control) = (SWDT_CONTROL_CKEY | (0xFFF << SWDT_CONTROL_CRV_BIT)| SWDT_CONTROL_CLKSEL );


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

*(zynq_common.swdt_lpd + swdt_lpd_control) = (SWDT_CONTROL_CKEY | (0xFFF << SWDT_CONTROL_CRV_BIT)| SWDT_CONTROL_CLKSEL );

*(zynq_common.swdt_lpd + swdt_lpd_control) = (SWDT_CONTROL_CKEY | (0xFFF << SWDT_CONTROL_CRV_BIT) | SWDT_CONTROL_CLKSEL);

gemini-code-assist

Code Review

This pull request introduces watchdog (SWDT) support for the ZynqMP platform, including register definitions, initialization, and platform control handlers for enabling and reloading the watchdog. However, there are critical issues in the implementation: the SWDT_CONTROL_CKEY shift value is incorrect (should be shifted by 14 instead of 12), which prevents control register writes from taking effect. Additionally, the platform control handlers for setting watchdog reload and enable do not set the return value ret to 0 on success, causing them to incorrectly return an error code to the caller.

Important

The consumer version of Gemini Code Assist on GitHub is being sunset. Starting June 18, 2026, new organization installations will be blocked, and all code review activity will officially cease on July 17, 2026.
For more details on the timeline and next steps, please review the Help Documentation.

gemini-code-assist · 2026-06-15T12:56:39Z

+#define SWDT_MODE_WDEN       (0x1U)
+#define SWDT_MODE_RSTEN      (0x1U << 1)
+#define SWDT_MODE_RSTLN      (0x4U << 4) /* reset len = 4 -> 32 clock cycles*/
+#define SWDT_CONTROL_CKEY    (SWDT_CKEY << 12)


In the ZynqMP SWDT Control Register (WDG_CONTROL), the CKEY field is located at bits [25:14], while the CRV (Counter Reload Value) field is at bits [13:2] (12 bits), and CLKSEL is at bits [1:0]. Shifting SWDT_CKEY (0x248) by 12 instead of 14 will result in an incorrect key being written to the register, causing the hardware to ignore any writes to the control register. This prevents both watchdog initialization and subsequent reload value updates from taking effect.

#define SWDT_CONTROL_CKEY (SWDT_CKEY << 14)

gemini-code-assist · 2026-06-15T12:56:40Z

+			if ((data->action == pctl_set) && (data->wdg_enable.enable == 1)) {
+				*(zynq_common.swdt_lpd + swdt_lpd_restart) = SWDT_RESTART_RKEY;
+				*(zynq_common.swdt_lpd + swdt_lpd_mode) = (SWDT_MODE_ZKEY | SWDT_MODE_RSTLN | SWDT_MODE_RSTEN | SWDT_MODE_WDEN);
+			}
+			else if ((data->action == pctl_set) && (data->wdg_enable.enable == 0)) {
+				*(zynq_common.swdt_lpd + swdt_lpd_restart) = SWDT_RESTART_RKEY;
+				*(zynq_common.swdt_lpd + swdt_lpd_mode) = (SWDT_MODE_ZKEY);
+			}


When performing a pctl_set action for pctl_wdg_enable, the return value ret is not set to 0 upon success. Since ret is initialized to -1, the function will return -1 (error) to the caller even when the enable/disable operation succeeded.

if ((data->action == pctl_set) && (data->wdg_enable.enable == 1)) { *(zynq_common.swdt_lpd + swdt_lpd_restart) = SWDT_RESTART_RKEY; *(zynq_common.swdt_lpd + swdt_lpd_mode) = (SWDT_MODE_ZKEY | SWDT_MODE_RSTLN | SWDT_MODE_RSTEN | SWDT_MODE_WDEN); ret = 0; } else if ((data->action == pctl_set) && (data->wdg_enable.enable == 0)) { *(zynq_common.swdt_lpd + swdt_lpd_restart) = SWDT_RESTART_RKEY; *(zynq_common.swdt_lpd + swdt_lpd_mode) = (SWDT_MODE_ZKEY); ret = 0; }

+			break;
+
+		case pctl_wdg_enable:
+			if ((data->action == pctl_set) && (data->wdg_enable.enable == 1)) {


+				*(zynq_common.swdt_lpd + swdt_lpd_restart) = SWDT_RESTART_RKEY;
+				*(zynq_common.swdt_lpd + swdt_lpd_mode) = (SWDT_MODE_ZKEY | SWDT_MODE_RSTLN | SWDT_MODE_RSTEN | SWDT_MODE_WDEN);
+			}
+			else if ((data->action == pctl_set) && (data->wdg_enable.enable == 0)) {


+			}
+			else if (data->action == pctl_get) {
+				ret = 0;
+				data->wdg_enable.enable = (*(zynq_common.swdt_lpd + swdt_lpd_mode) & SWDT_MODE_WDEN) ? 1 : 0;


+			}
+			else if (data->action == pctl_get) {
+				ret = 0;
+				data->wdg_enable.enable = (*(zynq_common.swdt_lpd + swdt_lpd_mode) & SWDT_MODE_WDEN) ? 1 : 0;


github-actions · 2026-06-15T13:12:35Z

Unit Test Results

10 860 tests +275 10 190 ✅ +275 53m 6s ⏱️ +58s
670 suites + 21 670 💤 ± 0
1 files ± 0 0 ❌ ± 0

Results for commit a6bb355. ± Comparison against base commit 57b3041.

This pull request removes 3 and adds 278 tests. Note that renamed tests count towards both.

phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit
phoenix-rtos-tests/libcache/unit ‑ armv7m7-imxrt106x-evk:phoenix-rtos-tests/libcache/unit
phoenix-rtos-tests/libcache/unit ‑ armv7m7-imxrt117x-evk:phoenix-rtos-tests/libcache/unit

phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_cleanCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_flushCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_read_readCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_write_readCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_callback_err.cache_write_writeCallbackErr
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_clean.cache_clean_addrOutOfScope
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_clean.cache_clean_addrPartiallyInScope
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_clean.cache_clean_badAddrRange
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_clean.cache_clean_lines
phoenix-rtos-tests/libcache/unit ‑ armv7m4-stm32l4x6-nucleo:phoenix-rtos-tests/libcache/unit.test_deinit.cache_deinit_initalizedCache
…

♻️ This comment has been updated with latest results.

- platformctl for reload and enable YT: DO-836

kber-ps · 2026-06-15T13:50:08Z

/gemini review

gemini-code-assist

Code Review

This pull request introduces support for the System Watchdog Timer (SWDT) on the ZynqMP platform, including initialization, reload, and enable/disable controls via hal_platformctl. However, two issues were identified: the register offsets defined in zynqmp_regs.h are incorrect due to a gap between the mode and control registers, which will lead to writing to incorrect registers, and there is a mismatch in SWDT_MODE_RSTLN where the value 4 is used instead of 3 for a 32-clock-cycle reset pulse length.

Important

The consumer version of Gemini Code Assist on GitHub is being sunset. Starting June 18, 2026, new organization installations will be blocked, and all code review activity will officially cease on July 17, 2026.
For more details on the timeline and next steps, please review the Help Documentation.

gemini-code-assist · 2026-06-15T13:52:19Z

+	swdt_lpd_mode = 0x00,
+	swdt_lpd_control,
+	swdt_lpd_restart,
+	swdt_lpd_status


The register offsets defined in the enum are incorrect. In the ZynqMP SWDT, there is a gap between the mode register (offset 0x00) and the control register (offset 0x08). Since these are used as indices for a volatile u32 * pointer, the enum values must represent the word offsets (index) of each register. Currently, swdt_lpd_control is implicitly assigned 1 (which corresponds to byte offset 0x04, a reserved area), and swdt_lpd_restart is assigned 2 (which corresponds to byte offset 0x08, the control register). This will cause watchdog configuration and reload operations to write to the wrong registers.

Suggested change

swdt_lpd_mode = 0x00,

swdt_lpd_control,

swdt_lpd_restart,

swdt_lpd_status

swdt_lpd_mode = 0x00,

swdt_lpd_control = 0x02,

swdt_lpd_restart = 0x03,

swdt_lpd_status = 0x04

julianuziemblo · 2026-06-16T13:31:24Z

+		struct {
+			__u32 reload;
+		} wdg_reload;
+
+		struct {
+			__u8 enable;
+		} wdg_enable;


nitpick: I could be wrong on this, but wouldn't it be clearer to do something like this:

union { __u32 reload; __u8 enable; } wdg;

Then again, all the other options have corresponding structures (except for mioclock which I guess belongs to mio structure?)...

julianuziemblo · 2026-06-16T13:36:22Z


+		case pctl_wdg_reload:
+			/* If watchdog is not enabled this will take no effects*/
+			if ((data->action == pctl_set) && (data->wdg_reload.reload >= 0x000FFFU) && (data->wdg_reload.reload <= 0xFFFFFFU)) {


returning -EINVAL in case the latter 2 conditions are wrong could be more informative to the user

julianuziemblo · 2026-06-16T13:57:01Z

+		case pctl_wdg_reload:
+			/* If watchdog is not enabled this will take no effects*/
+			if ((data->action == pctl_set) && (data->wdg_reload.reload >= 0x000FFFU) && (data->wdg_reload.reload <= 0xFFFFFFU)) {
+				*(zynq_common.swdt_lpd + swdt_lpd_control) = (SWDT_CONTROL_CKEY | ((data->wdg_reload.reload >> 12) & 0xFFFU) << SWDT_CONTROL_CRV_BIT | SWDT_CONTROL_CLKSEL);


nitpick: add parenthesis over ((data->wdg_reload.reload >> 12) & 0xFFFU) << SWDT_CONTROL_CRV_BIT

ZynqMP RPU Watchdog handler

228f1dc

- kernel level watchdog initialization - reload value in board_config.h for user - watchdog prescaler set to 512 (LPD_LSBUS_CLK) - RPU reset on timeout - syscall for reload YT: DO-836

github-actions Bot reviewed Jun 15, 2026

View reviewed changes

gemini-code-assist Bot reviewed Jun 15, 2026

View reviewed changes

github-advanced-security AI found potential problems Jun 15, 2026

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ZynqMP RPU Watchdog handler

a6bb355

- platformctl for reload and enable YT: DO-836

kber-ps force-pushed the kber/zynqmp_rpu_wdg branch from 251770b to a6bb355 Compare June 15, 2026 13:47

kber-ps requested a review from agkaminski June 15, 2026 13:51

gemini-code-assist Bot reviewed Jun 15, 2026

View reviewed changes

julianuziemblo reviewed Jun 16, 2026

View reviewed changes

	*(zynq_common.swdt_lpd + swdt_lpd_control) = (SWDT_CONTROL_CKEY \| (0xFFF << SWDT_CONTROL_CRV_BIT)\| SWDT_CONTROL_CLKSEL );
	*(zynq_common.swdt_lpd + swdt_lpd_control) = (SWDT_CONTROL_CKEY \| (0xFFF << SWDT_CONTROL_CRV_BIT) \| SWDT_CONTROL_CLKSEL);

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kber-ps commented Jun 15, 2026

Description

Motivation and Context

Types of changes

How Has This Been Tested?

Checklist:

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github-actions Bot commented Jun 15, 2026 •

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