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@programmable-logic-tools Programmable Logic Tools

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    21 repositories

    • altera-max7000-db

      Public
      This project has moved here: https://github.com/programmable-logic-tools/altera-max-db
      HTML
      •0•0•0•0•Updated Mar 22, 2026Mar 22, 2026

    • altera-max-db

      Public
      Third-party bitstream documentation for Altera MAX7000 CPLDs
      Verilog
      •
      GNU Affero General Public License v3.0
      •0•7•1•0•Updated Mar 20, 2026Mar 20, 2026

    • altera-max-tools

      Public
      Third-party software tools for Altera MAX CPLDs
      C++
      •
      GNU Affero General Public License v3.0
      •0•8•0•0•Updated Mar 18, 2026Mar 18, 2026

    • terasic-usb-blaster

      Public
      Inofficial KiCad 5 schematic for Terasic's USB-Blaster (JTAG debugger) for Altera CPLDs and FPGAs
      0•11•0•0•Updated Feb 27, 2025Feb 27, 2025

    • xc2064

      Public
      Reverse engineering the XC2064 FPGA
      JavaScript
      •6•0•0•0•Updated Aug 14, 2021Aug 14, 2021

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •1.1k•0•0•0•Updated Jan 10, 2021Jan 10, 2021

    • logic-block-library

      Public
      A library of basic building blocks for programmable logic designs
      Verilog
      •
      GNU Affero General Public License v3.0
      •2•1•0•0•Updated Jan 9, 2021Jan 9, 2021

    • icestorm

      Public
      Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
      Python
      •
      ISC License
      •237•2•0•0•Updated Sep 3, 2020Sep 3, 2020

    • python-netlists

      Public
      Python libraries to help writing pin constraints files for programmable logic projects
      Python
      •
      GNU Affero General Public License v3.0
      •0•0•0•0•Updated Jul 20, 2020Jul 20, 2020

    • atmel-atdh1150usb

      Public
      Inofficial KiCad 5 schematic for Atmel's ATDH1150USB(-K) JTAG debugger for CPLDs
      0•9•0•0•Updated Jan 20, 2019Jan 20, 2019

    • tachyon-cvc

      Public
      Inofficial mirror of Tachyon DA's CVC Verilog to Executable compiler
      C
      •27•0•0•0•Updated Jan 14, 2019Jan 14, 2019

    • galasm-daveho

      Public
      Very slightly modified version of Alessandro Zummo's GALasm 2.1, for programming GAL devices
      HTML
      •78•0•0•0•Updated Jan 5, 2019Jan 5, 2019

    • lattice-xp2-standard-playground

      Public
      Lattice XP2 Standard evaluation board Diamond playground
      TeX
      •0•0•0•0•Updated Dec 7, 2018Dec 7, 2018

    • spartan-doc

      Public
      Technical documentation required for understanding how Xilinx Spartan FPGAs work and must be programmed
      Makefile
      •0•1•0•0•Updated Aug 11, 2018Aug 11, 2018

    • galasm-dwery

      Public
      Portable GAL Assembler
      HTML
      •9•0•0•0•Updated May 19, 2018May 19, 2018

    • flashrom-ice40

      Public
      Flashes FPGA bitmaps onto Lattice iCE40 evaluation board through the onboard FTDI-2232H
      C
      •
      GNU General Public License v2.0
      •491•0•1•0•Updated Feb 12, 2018Feb 12, 2018

    • veditor

      Public
      Eclipse Verilog/VHDL Editor - a fork of the SourceForge repository
      Java
      •1•1•0•0•Updated Jul 23, 2016Jul 23, 2016

    • jtag-signal-debugger

      Public
      FPGA-based tool to analyze and debug JTAG connections
      VHDL
      •1•0•0•0•Updated Aug 19, 2015Aug 19, 2015

    • VHDL-Visualizer

      Public
      A little JavaScript magic to convert VHDL source into a neat block diagram
      HTML
      •3•5•0•0•Updated Aug 17, 2015Aug 17, 2015

    • bluefish-vhdl

      Public
      VHDL syntax highlighting definition for the Bluefish editor
      GNU General Public License v3.0
      •0•0•0•0•Updated May 19, 2015May 19, 2015

    • galpal

      Public
      Verilog models for the GAL22V10 and select PAL devices.
      Verilog
      •4•0•0•0•Updated Jan 29, 2015Jan 29, 2015
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