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    48 repositories

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •1.1k•0•0•2•Updated May 2, 2026May 2, 2026

    • sv-tests-pvt-results

      Public
      Output of the sv-tests runs.
      HTML
      •6•0•0•0•Updated May 2, 2026May 2, 2026

    • OpenSTA

      Public
      OpenSTA Silimate fork
      C++
      •
      GNU General Public License v3.0
      •58•3•0•0•Updated May 2, 2026May 2, 2026

    • liberty2json

      Public
      Liberty to JSON converter
      converterjsonliberty
      converterjsonlibertyopensta
      Verilog
      •
      GNU General Public License v3.0
      •0•3•0•0•Updated Apr 29, 2026Apr 29, 2026

    • silisizer

      Public
      Operator resize
      Verilog
      •
      GNU General Public License v3.0
      •3•1•0•0•Updated Apr 29, 2026Apr 29, 2026

    • OpenROAD

      Public
      OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •876•0•0•0•Updated Apr 17, 2026Apr 17, 2026

    • homebrew-silimate

      Public
      Silimate Homebrew tap
      Ruby
      •
      MIT License
      •0•0•0•0•Updated Apr 16, 2026Apr 16, 2026

    • abc

      Public
      ABC: System for Sequential Logic Synthesis and Formal Verification
      C
      •
      Other
      •745•0•0•1•Updated Apr 11, 2026Apr 11, 2026

    • sv-tests

      Public
      Test suite designed to check compliance with the SystemVerilog standard.
      SystemVerilog
      •
      ISC License
      •91•0•0•0•Updated Mar 27, 2026Mar 27, 2026

    • iverilog

      Public
      Icarus Verilog
      C++
      •
      GNU General Public License v2.0
      •595•0•0•0•Updated Mar 23, 2026Mar 23, 2026

    • rtlmeter

      Public
      RTLMeter benchmark suite
      Verilog
      •
      Apache License 2.0
      •12•0•0•0•Updated Mar 9, 2026Mar 9, 2026

    • turtle

      Public
      TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)
      Python
      •
      Apache License 2.0
      •8•0•0•0•Updated Mar 9, 2026Mar 9, 2026

    • cvdp_benchmark

      Public
      Framework for evaluating LLM and agent solutions on hardware verification challenges
      Python
      •
      Apache License 2.0
      •45•0•0•0•Updated Mar 9, 2026Mar 9, 2026

    • Nuitka

      Public
      Nuitka is a Python compiler written in Python. It's fully compatible with Python 2.6, 2.7, 3.4-3.13. You feed it your Python app, it does a lot of clever thing…
      Python
      •
      GNU Affero General Public License v3.0
      •773•0•0•0•Updated Mar 6, 2026Mar 6, 2026

    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      SystemVerilog
      •
      Apache License 2.0
      •726•0•0•0•Updated Mar 5, 2026Mar 5, 2026

    • prunefl

      Public
      SystemVerilog file list pruner
      C++
      •
      MIT License
      •1•18•0•0•Updated Mar 2, 2026Mar 2, 2026

    • vcd2fst

      Public
      Convert VCD waveform file to FST waveform file
      C
      •1•1•0•0•Updated Mar 2, 2026Mar 2, 2026

    • bounties

      Public archive
      Open-source silicon bounties
      0•1•3•0•Updated Mar 1, 2026Mar 1, 2026

    • slang-server

      Public
      A SystemVerilog language server based on the Slang parser and library.
      C++
      •
      MIT License
      •35•0•0•0•Updated Feb 13, 2026Feb 13, 2026

    • logikbench

      Public
      Parametrized suite of Verilog RTL benchmarks.
      Verilog
      •
      MIT License
      •4•0•0•0•Updated Feb 13, 2026Feb 13, 2026

    • yosys-slang

      Public
      SystemVerilog frontend for Yosys
      C++
      •
      ISC License
      •43•0•0•0•Updated Feb 13, 2026Feb 13, 2026

    • FakeRAM2.0

      Public
      Python
      •18•0•0•0•Updated Feb 13, 2026Feb 13, 2026

    • chimera

      Public
      A tool for synthesizing Verilog programs
      Verilog
      •
      GNU General Public License v3.0
      •14•1•0•0•Updated Feb 13, 2026Feb 13, 2026

    • smdb-ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      SystemVerilog
      •
      Apache License 2.0
      •726•0•0•0•Updated Feb 2, 2026Feb 2, 2026

    • ChipBench

      Public
      A comprehensive benchmark for AI-aided chip design
      SystemVerilog
      •
      Other
      •4•0•0•0•Updated Jan 29, 2026Jan 29, 2026

    • slang

      Public
      SystemVerilog compiler and language services
      C++
      •
      MIT License
      •221•0•0•0•Updated Jan 22, 2026Jan 22, 2026

    • VlogHammer

      Public
      A Verilog Synthesis Regression Test
      Shell
      •
      ISC License
      •12•2•0•0•Updated Jan 19, 2026Jan 19, 2026

    • sv-tests-results

      Public
      Output of the sv-tests runs.
      HTML
      •6•0•0•0•Updated Jan 15, 2026Jan 15, 2026

    • pruneccs

      Public
      Prune CCS data out of Liberty file for more compact files
      C++
      •
      GNU General Public License v3.0
      •1•0•0•0•Updated Jan 2, 2026Jan 2, 2026

    • coralnpu

      Public
      A machine learning accelerator core designed for energy-efficient AI at the edge.
      Emacs Lisp
      •
      Apache License 2.0
      •273•0•0•0•Updated Dec 30, 2025Dec 30, 2025
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