8385588: Tune APX support in C2 backend

[dwhite-intel]

For the latest Intel processors with APX support, HW architects recommend a different balance of APX and legacy instructions for best performance.

This patch removes support for:

NDD instructions with memory-based operands
APX version of SETZUcc

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Progress

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Issue

• JDK-8385588: Tune APX support in C2 backend (Enhancement - P4)

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[mlbridge]

Webrevs

• 00: Full (a7e922d0)

[sviswa7]

Wondering if we should add an instruct:

instruct cmovI_memUCFE(cmpOpUCFE cop, rFlagsRegUCFE cr, rRegI dst, memory src) %{
  match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));

  ins_cost(250);
  expand %{
    __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
  %}
%}

[sviswa7]

Wondering if we should add an instruct:

instruct cmovL_memUCFE(cmpOpUCFE cop, rFlagsRegUCFE cr, rRegL dst, memory src) %{
  match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));

  ins_cost(200);
  expand %{
     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
  %}
%}