DFTLint

Find DFT problems before they become expensive scan-insertion and ATPG problems.

DFTLint analyzes a Yosys JSON netlist and reports structural testability problems with concrete next actions. It emits terminal, JSON, and SARIF reports for local use and CI.

Status: early development. DFTLint is a quality and learning tool, not a replacement for production DFT signoff.

What It Catches

• Sequential clocks and asynchronous resets that are not test-controllable
• Missing top-level scan ports
• Non-scan sequential cells when full scan is required
• Missing or tied-off scan inputs and scan-enable pins
• Mixed scan-clock domains
• Scan cells with orphaned chain inputs or outputs

See the complete rule catalog.

Quick Start

DFTLint requires Python 3.11 or newer and has no runtime dependencies.

python3 -m pip install -e .

dftlint analyze examples/good_scan/design.json \
  --config examples/good_scan/config.toml

Expected result:

DFTLint: good_scan
Sequential cells: 2  Scan cells: 2  Findings: 0 (0 errors, 0 warnings)

No findings.

Now inspect the intentionally broken example:

dftlint analyze examples/broken_scan/design.json \
  --config examples/broken_scan/config.toml --fail-on none

The report identifies uncontrolled clocks and resets, missing scan ports, a non-scan flop, tied scan controls, and a broken chain output.

Generate Input With Yosys

read_verilog rtl/top.v
hierarchy -check -top top
proc
write_json build/top.json

Then create dftlint.toml:

[design]
top = "top"

[test]
controllable_clocks = ["test_clk"]
controllable_resets = ["test_reset_n"]
scan_enable_ports = ["scan_enable"]
scan_in_ports = ["scan_in"]
scan_out_ports = ["scan_out"]
require_scan_ports = true
require_all_scan = true
allow_mixed_scan_clocks = false

Run the analysis:

dftlint analyze build/top.json --config dftlint.toml

The default exit code is 1 when an error-level finding exists. Change the quality gate with --fail-on none, --fail-on warning, or --fail-on error.

Reports

JSON for scripts:

dftlint analyze build/top.json --config dftlint.toml \
  --format json --output reports/dftlint.json

SARIF for GitHub code scanning:

dftlint analyze build/top.json --config dftlint.toml \
  --format sarif --output reports/dftlint.sarif

GitHub Action

This repository includes a composite action:

permissions:
  contents: read
  security-events: write

steps:
  - uses: actions/checkout@v6
  - uses: YosysHQ/setup-oss-cad-suite@v3
  - run: yosys -p "read_verilog rtl/top.v; hierarchy -top top; proc; write_json top.json"
  - uses: narjun4394/dftlint@main
    with:
      design: top.json
      config: dftlint.toml
      output: dftlint.sarif
  - uses: github/codeql-action/upload-sarif@v3
    with:
      sarif_file: dftlint.sarif

CLI

dftlint analyze DESIGN [--config FILE] [--top MODULE]
                       [--format text|json|sarif] [--output FILE]
                       [--fail-on none|warning|error]

dftlint rules

Current Limits

• Input is Yosys JSON; DFTLint does not invoke Yosys yet.
• Cell and pin recognition uses common naming conventions.
• Rules are structural and do not generate ATPG patterns or fault coverage.
• Hierarchical and library-specific analysis needs more work.

These are intentional MVP boundaries. The next major step is configurable library cell maps followed by OpenROAD scan-chain import.

Development

python3 -m unittest discover -s tests -v
python3 -m compileall -q src tests

See CONTRIBUTING.md and the original project research.

License

MIT