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1. RISC-V32 RISC-V32 Public

   5-stage pipelined RV32I processor in Verilog with UART interface, branch prediction, and hazard handling — targeting Cyclone IV FPGA.

   Verilog 1

2. UART UART Public

   This project is the final project of the NTI training on Digtial Design Using FPGA

   Verilog

3. asst1 asst1 Public

   Forked from stanford-cs149/asst1

   My fork of Stanford CS149 -- Assignment 1

   C++

4. fpga-design-toolkit fpga-design-toolkit Public

   Forked from moaz-kh/fpga-design-toolkit

   FPGA design toolkit

   Shell