ChipGate Phase 31K Real Toolchain Evidence v0

Recent ChipGate evidence: Phase 31K now runs in Docker with real Yosys synthesis and nextpnr-ice40 timing.

In this public toolchain run, DTL_FASTPATH preserved the configured safety gate while reporting:

• 8 synthesized cells
• 6 iCE40 logic cells
• 1.596 ns timing
• 626.566 MHz Fmax

Compared with the classic safe FSM baseline under the same Docker/Yosys/nextpnr flow:

• 66.7% fewer cells
• 60% fewer logic cells
• 172% higher Fmax

Compared with the classic redundant wrapper, the result is mixed but useful:

• 50% fewer cells
• 45.455% fewer logic cells
• 3.07% lower Fmax

Honest boundary: DTL_FASTPATH was much smaller and much faster than the classic safe FSM baseline, and smaller than the redundant safe wrapper, but not faster than the redundant wrapper on this nextpnr-ice40 timing run.

Blocked claims remain blocked: ASIC/OpenSTA timing, real silicon performance, fabrication readiness, production readiness, safety certification, and universal chip-performance claims are not claimed by this release.

ChipGate Phase 31K OpenSTA Toolchain v2

This release records the OpenSTA toolchain unlock for ChipGate Phase 31K.

Fresh Docker evidence:

• OpenSTA installed from upstream source build.
• sta -version: 3.1.0.
• python3 -m chipgate nodeshrink-real --detect reports opensta_available: true and opensta_path: /usr/local/bin/sta.
• Yosys remains available.
• nextpnr-ice40 remains available.
• Container pytest passed: 4 passed.

Current benchmark evidence remains:

• Synthesis: REAL_SYNTHESIS_EVIDENCE.
• Timing: REAL_NEXTPNR_TIMING_EVIDENCE.
• DTL_FASTPATH: 8 cells, 6 iCE40 logic cells, 1.596 ns, 626.566 MHz.

Boundary:

OpenSTA is now available in the Docker image, but the published Phase 31K timing numbers are still nextpnr-ice40 timing metrics. ASIC/OpenSTA timing metrics remain blocked until an ASIC Liberty/SDC target is added and measured.

ChipGate Phase 31K Claim Boundary v1

This release adds the explicit public claim boundary after a fresh Docker rerun of ChipGate Phase 31K.

Fresh Docker verification:

• Docker build passed.
• Container pytest passed: 4 passed.
• Yosys available: true.
• nextpnr-ice40 available: true.
• OpenSTA available: false.
• Evidence status: REAL_SYNTHESIS_EVIDENCE and REAL_NEXTPNR_TIMING_EVIDENCE.

Safe result summary:

• DTL_FASTPATH: 8 cells, 6 iCE40 logic cells, 1.596 ns timing, 626.566 MHz.
• Vs CLASSIC_SAFE_FSM: 66.667% fewer cells, 60% fewer logic cells, 172.18% higher Fmax.
• Vs CLASSIC_REDUNDANT: 50% fewer cells, 45.455% fewer logic cells, 3.07% lower Fmax.

Claims still blocked:

• DTL beats all chips.
• DTL beats NVIDIA.
• DTL proves real silicon.
• DTL proves ASIC timing.
• DTL is production ready.
• DTL is universally faster.
• DTL is safety certified.

Reason: OpenSTA was unavailable, ASIC/static timing evidence is still missing, this is nextpnr-ice40 FPGA-style timing evidence, and no real silicon fabrication/test evidence exists yet.