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README.md
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alu1.vhd
alu1.vhd
 
 
alu2.vhd
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d_fetch.vhd
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dc_fetch.vhd
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dc_fifo.vhd
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dc_mem.vhd
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dc_mux.vhd
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dcmd_fifo.vhd
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dcontrol.vhd
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decode.vhd
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dlookahead.vhd
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dtag_fetch.vhd
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i_fetch.vhd
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ic_fetch.vhd
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ic_fifo.vhd
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ic_mux.vhd
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icmd_fifo.vhd
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icontrol.vhd
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ilookahead.vhd
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iodrp_controller.vhd
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iodrp_mcb_controller.vhd
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jump.vhd
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l_mux.vhd
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mcb.vhd
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mcb_raw_wrapper.vhd
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mcb_soft_calibration.vhd
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mcb_soft_calibration_top.vhd
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memc3_infrastructure.vhd
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memc3_wrapper.vhd
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octagon.vhd
octagon.vhd
 
 
octagon_funcs.vhd
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octagon_posttran.vhd
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octagon_test.vhd
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octagon_types.vhd
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pc_module.vhd
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pc_module_test.vhd
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r_fetch.vhd
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r_store.vhd
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store.vhd
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tag_fetch.vhd
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top.vhd
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top2.vhd
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wb_master.vhd
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wbreader.vhd
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xilinx_top.vhd
xilinx_top.vhd
 
 

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octagon

Octagon is a largely MIPS compatible soft-core for fpga's. It it optimized for Xilinx LUT-6 architectures and uses a memory interface similar to MiG generated cores. Required compiler flags are detailed in the code subdirectory.

Processor is an 8 thread barrel processor. Supporting 1 interrupt mask per thread which can be used by a GIC implemented on the wishbone controller.

Top module of processor is octagon.vhd

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