This repository contains practice material for lectures on UVM.
The starting point is a RISC-V Single-Cycle core with a directed test.
Through the practice sessions, students will add the necessary code required for a minimal UVM testbench.
Clone this repo on a Linux machine with a valid Questa license. The license is mandatory.
You must be able to use vlog and vsim and have the all the UVM libraries installed already.
Then, navigate to the tutorials folder and follow all the instructions in order.
- Spear, C., & Tumbush, G. (2012). SystemVerilog for verification: A guide to learning the testbench language features (3rd ed.). New York, NY: Springer.
- Salemi, R. (2013). The UVM primer: A step-by-step introduction to the Universal Verification Methodology. Boston, MA: Boston Light Press.