[SYCL] PR 4 - Remove FPGA Attributes from SYCL FE#21756
Merged
KornevNikita merged 2 commits intointel:syclfrom Apr 15, 2026
Merged
[SYCL] PR 4 - Remove FPGA Attributes from SYCL FE#21756KornevNikita merged 2 commits intointel:syclfrom
KornevNikita merged 2 commits intointel:syclfrom
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Fznamznon
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Apr 14, 2026
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I'm concerned that these PR's are growing bigger. This one is already 3814 lines.
Otherwise, some dead code is left behind.
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| SmallString<256> AnnotStr; | ||
| CGM.generateIntelFPGAAnnotation(field, AnnotStr); | ||
| if (!AnnotStr.empty()) | ||
| addr = EmitIntelFPGAFieldAnnotations(field, addr, AnnotStr); |
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Same here, the whole block is dead code now
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I will try to keep the others smaller. As I started working on this subset, the clique just got bigger. |
Fznamznon
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Apr 15, 2026
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@intel/llvm-gatekeepers please consider merging |
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@premanandrao could you please resolve conflicts |
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@KornevNikita, conflicts have been resolved and the tests are clean again. Thanks! |
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This removes the following attributes:
[[intel::doublepump]]
[[intel::singlepump]]
[[intel::fpga_memory]]
[[intel::fgpa_register]]
[[intel::bankwidth]]
[[intel::numbanks]]
[[intel::private_copies]]
[[intel::merge]]
[[intel::max_replicates]]
[[intel::simple_dual_port]]
[[intel::bank_bits]]
[[intel::force_pow2_depth]]