migration D (C2 wave 1): reversible VM opcodes (4 kernels, 4-gate green)#536
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Deep wave 2 of the ReScript -> AffineScript -> wasm migration. Cluster C2
(the vm/lib/ocaml reversible instruction set) wave 1: the value-transform
opcodes re-decomposed into four pure-integer kernels staged under
proposals/idaptik/migrated/, each verified by the 4-gate recipe.
The VM stores state in a dict<int> keyed by register NAME, with each
instruction a pair of execute/invert closures. Re-decomposition: the register
names + dict stay host-side (the senses); the brain is the reversible scalar-int
VALUE transform per opcode. "The integer IS the register."
The defining VM invariant is reversibility (invert undoes execute). It is pinned
directly as *_roundtrip exports whose oracle is the identity, and swept in Gate 2
over i32 extremes.
VmArith ADD/SUB (inverse pair), NEGATE/NOOP/SWAP (self-inverse)
VmBitwise FLIP/XOR (self-inverse), ROL/ROR (inverse pair, 32-bit)
VmAncilla AND/OR via Bennett's ancilla (reversible iff ancilla c == 0)
VmInstruction 23-opcode instruction-set encoding + tier classifier
Four gates green (captured in migrated/EVIDENCE-C2.adoc):
G1 compile 4/4 -> wasm
G2 parity 2100/2100 oracle-vs-wasm inputs, incl. every reversibility
round-trip (inverse undoes execute) over i32 extremes
G3 echo-boundary VmInstruction 23-opcode encoding LOSSLESS (agda exit 0)
G4 assail 4/4 clean
Three AffineScript backend facts surfaced and worked around (recorded in
EVIDENCE-C2.adoc as findings):
* unary ~ mis-compiles (i32.xor missing an operand) -> FLIP uses the
two's-complement identity ~a == -a - 1 (verified equal, self-inverse);
* >> is arithmetic and >>> does not exist, but ROL/ROR need a logical shift
right -> emulated as (a >> n) & ((1 << (32 - n)) - 1); rotations then match
JS ((a<<n)|(a>>>(32-n)))|0 and round-trip over the full i32 range;
* << and i32 wrap are correct (the VM's word model).
The unary-~ bug is a candidate Phase-F compiler fix.
AND/OR are the honest outlier: reversible only via Bennett's ancilla trick and
only under the declared precondition that the ancilla starts at 0; every other
opcode here is unconditionally reversible.
Wave 2 (deferred — needs an array/linear-memory ABI + control-flow model):
Mul/Div, stack/memory (Push/Pop/Load/Store), control (Call/Loop/IfPos/IfZero),
I/O (Send/Recv/CoprocessorCall), and the structural VM files (State, VM,
SubroutineRegistry, *Coprocessor, bindings).
Ledger: Phase D (C2 wave 1) DONE; migration-map.json C2 -> IN_PROGRESS with the
wave-1 detail. Staged, not applied (idaptik write-access gate, Phase Omega).
https://claude.ai/code/session_01WoKhFQePiRsAj7aqnxbG8s
🔍 Hypatia Security ScanFindings: 87 issues detected
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Phase D / cluster C2 wave 1 of the ReScript → AffineScript → wasm migration of
hyperpolymath/idaptik. Continues #535 (Phase B + C1, merged). Staged underproposals/idaptik/migrated/— verified + applyable, not applied (idaptik write-access gate).What landed — the reversible VM value-transform opcodes
The VM stores state in a
dict<int>keyed by register name, each instruction a pair ofexecute/invertclosures. Re-decomposition: names + dict stay host-side (senses); the brain is the reversible scalar-int value transform per opcode.VmArithVmBitwiseVmAncillaVmInstructionThe defining VM invariant —
invert ∘ execute = id— is pinned as explicit*_roundtripexports (oracle = identity) and swept over i32 extremes.Four gates green (
migrated/EVIDENCE-C2.adoc)0x55555555/0xAAAAAAAAand overflow)VmInstruction23-opcode encoding Agda-certified LOSSLESS (agda exit 0)Compiler findings (worked around; recorded as findings)
Migrating the bitwise opcodes surfaced three AffineScript backend facts:
~mis-compiles — emitsi32.xorwith a missing operand (the wasm won't instantiate). Isolated to unary~;&/|/^are sound. → FLIP uses~a == -a-1(verified equal + self-inverse). Candidate Phase-F compiler fix.>>is arithmetic and>>>doesn't exist, but ROL/ROR need a logical shift-right → emulatedlsr(a,n) = (a>>n) & ((1<<(32-n))-1); rotations then match JS((a<<n)|(a>>>(32-n)))|0and round-trip over the full i32 range.<<and i32 wrap are correct (the VM's word model).AND/ORare the honest outlier — reversible only via Bennett's ancilla trick under a declared precondition (ancilla starts at 0); every other opcode here is unconditionally reversible.Ledger
Phase D (C2 wave 1) DONE;
migration-map.jsonC2 → IN_PROGRESS with the wave-1 detail. NEXT: C2 wave 2 — Mul/Div, stack/memory (Push/Pop/Load/Store), control flow (Call/Loop/IfPos/IfZero), I/O (Send/Recv/CoprocessorCall) and the structural VM files; these need an array/linear-memory ABI.On top of current
main(d706d52, post-#535).https://claude.ai/code/session_01WoKhFQePiRsAj7aqnxbG8s
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