feat(ir/dsl): MXFP8/MXFP4 tile DSL ops - #2117
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📝 WalkthroughWalkthroughAdds MX block-scale support for Ascend950, including FP8E8M0, scale memory spaces, MX matmul and quantization operators, Python APIs, PTO lowering, memory-layout handling, tests, and documentation. ChangesMX block-scale support
Estimated code review effort: 4 (Complex) | ~45 minutes Sequence Diagram(s)sequenceDiagram
participant DSL
participant TileIR
participant PTOCodegen
participant Ascend950
DSL->>TileIR: Load MX tensors and scales
DSL->>TileIR: Call tget_scale_addr and matmul_mx
TileIR->>PTOCodegen: Lower registered tile operations
PTOCodegen->>Ascend950: Emit MX PTO instructions
Possibly related issues
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🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
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💡 Codex Review
When users call pl.matmul_mx_acc, adding it to kSimpleOps sends it through MakeNaryCodegenPTO, which emits the IR-level accumulator as an ins(...) operand and the assignment target as a separate outs(...) buffer. The existing accumulator lowering below is custom because PTOAS expects the accumulator operand and output buffer to be the same SSA value; under tile-address/PyPTO-planner paths the result var can be a different tile_buf even when it shares the same MemRef, so this new op can generate invalid or non-accumulating MLIR. Please register it with an accumulator-specific lowering like tile.matmul_acc.
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Actionable comments posted: 4
Caution
Some comments are outside the diff and can’t be posted inline due to platform limitations.
⚠️ Outside diff range comments (2)
tests/ut/core/test_dtype.py (1)
248-254: 🎯 Functional Correctness | 🟡 Minor | ⚡ Quick winCover FP8E8M0’s non-integer invariant.
Line 254 verifies
is_float(), but FP8E8M0 is absent fromtest_is_intandtest_type_predicates_mutual_exclusion; a regression reporting both float and integer would pass. Add it to both negative/exclusivity lists.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@tests/ut/core/test_dtype.py` around lines 248 - 254, Add pypto.DT_FP8E8M0 to the non-integer assertions in test_is_int and to the mutually exclusive type-predicate checks in test_type_predicates_mutual_exclusion, ensuring it is validated as floating-point only.include/pypto/core/dtype.h (1)
71-82: 🎯 Functional Correctness | 🟡 Minor | ⚡ Quick winPreserve FP8E8M0 semantic separation in
IsFloat().
kFp8e8m0Code(0x36) falls inside the IEEE float range, soDataType::FP8E8M0.IsFloat()returnstrue. MX FP8E8M0 is block-scale exponent-only data rather than a general arithmetic float, and genericIsFloat()gates now accept it across arith simplification, constant folding, codegen, type inference, and tensor ops. Use a specific MX/block-scale predicate for MX call sites such astile.tdequant, rather than relying on the broad range check.🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the rest with a brief reason, keep changes minimal, and validate. In `@include/pypto/core/dtype.h` around lines 71 - 82, Update DataType::IsFloat() so kFp8e8m0Code is excluded from the general IEEE float classification despite falling within kIeeeFloatRangeStart–kIeeeFloatRangeEnd. Add or use a dedicated MX/block-scale predicate for FP8E8M0, and update MX-specific callers such as tile.tdequant to use it instead of IsFloat(), while preserving IsFloat() for arithmetic floating-point types.
🤖 Prompt for all review comments with AI agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
Inline comments:
In `@docs/en/dev/ptoas-op-status.md`:
- Line 124: Update the four PTOAS operation-status matrix entries to mark ST as
❌ and describe the coverage as PTOAS compilation only, not hardware execution:
docs/en/dev/ptoas-op-status.md lines 124-124 and 174-174, and
docs/zh-cn/dev/ptoas-op-status.md lines 117-117 and 167-167. Preserve the
existing frontend/codegen and device-execution-pending details where applicable.
In `@src/backend/common/pto_ops_datamove.cpp`:
- Around line 605-614: The MakeTQuantCodegenPTO lowering currently drops the
validated tile.tquant mode when emitting pto.tquant.mx. Update
MakeTQuantCodegenPTO and its generated PTOAS representation to preserve and emit
the mode attribute, or explicitly reject unsupported modes before lowering; do
not allow MXFP4/MXFP8 selections to reach PTOAS without mode information.
In `@src/ir/op/tile_ops/matmul.cpp`:
- Around line 407-464: Add explicit 2D shape checks in DeduceTileMatMulMxAccType
and DeduceTileMatMulMxBiasType immediately after validating the TileType and
before any shape_[0] or shape_[1] access. Require shape_.size() == 2 and use the
existing sibling non-MX functions’ validation pattern and clear
operator-specific error messages.
In `@src/ir/op/tile_ops/mx.cpp`:
- Around line 37-42: Update GetMxQuantOutDtype to reject unknown mode strings
instead of falling through to DataType::FP8E4M3FN. Preserve the existing
mappings for all five supported modes, and add the established IR-construction
error or validation path so invalid values such as "mxfp8_e5m3" fail fast with a
diagnostic.
---
Outside diff comments:
In `@include/pypto/core/dtype.h`:
- Around line 71-82: Update DataType::IsFloat() so kFp8e8m0Code is excluded from
the general IEEE float classification despite falling within
kIeeeFloatRangeStart–kIeeeFloatRangeEnd. Add or use a dedicated MX/block-scale
predicate for FP8E8M0, and update MX-specific callers such as tile.tdequant to
use it instead of IsFloat(), while preserving IsFloat() for arithmetic
floating-point types.
In `@tests/ut/core/test_dtype.py`:
- Around line 248-254: Add pypto.DT_FP8E8M0 to the non-integer assertions in
test_is_int and to the mutually exclusive type-predicate checks in
test_type_predicates_mutual_exclusion, ensuring it is validated as
floating-point only.
🪄 Autofix (Beta)
Fix all unresolved CodeRabbit comments on this PR:
- Push a commit to this branch (recommended)
- Create a new PR with the fixes
ℹ️ Review info
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Plan: Pro Plus
Run ID: 7050f4d6-6da3-4771-af65-bee8b74bd451
📒 Files selected for processing (45)
CMakeLists.txtdocs/en/dev/ir/05-operators.mddocs/en/dev/passes/16-infer_tile_memory_space.mddocs/en/dev/ptoas-op-status.mddocs/zh-cn/dev/ir/05-operators.mddocs/zh-cn/dev/passes/16-infer_tile_memory_space.mddocs/zh-cn/dev/ptoas-op-status.mdinclude/pypto/core/dtype.hinclude/pypto/ir/memory_space.hinclude/pypto/ir/pipe.hinclude/pypto/ir/tile_view_semantics.hinclude/pypto/ir/transforms/utils/attrs.hpython/bindings/modules/core.cpppython/bindings/modules/ir.cpppython/pypto/__init__.pypython/pypto/backend/pto_backend.pypython/pypto/ir/__init__.pypython/pypto/ir/__init__.pyipython/pypto/ir/compiled_program.pypython/pypto/ir/op/tile_ops.pypython/pypto/ir/type.pypython/pypto/jit/decorator.pypython/pypto/jit/specializer.pypython/pypto/language/__init__.pypython/pypto/language/op/__init__.pypython/pypto/language/op/tile_ops.pypython/pypto/language/parser/type_resolver.pypython/pypto/pypto_core/__init__.pyipython/pypto/pypto_core/ir.pyisrc/backend/common/pto_ops_datamove.cppsrc/backend/common/pto_ops_elementwise.cppsrc/backend/common/soc.cppsrc/codegen/pto/pto_codegen.cppsrc/codegen/pto/pto_type_utils.cppsrc/ir/memref.cppsrc/ir/op/tile_ops/matmul.cppsrc/ir/op/tile_ops/memory.cppsrc/ir/op/tile_ops/mx.cppsrc/ir/transforms/infer_tile_memory_space_pass.cppsrc/ir/transforms/memory_reuse_pass.cpptests/st/runtime/ops/test_matmul_mx.pytests/ut/codegen/test_mx_ops_codegen.pytests/ut/core/test_dtype.pytests/ut/ir/operators/test_mx_ops.pytests/ut/ir/operators/test_op_registry.py
💤 Files with no reviewable changes (1)
- src/ir/transforms/infer_tile_memory_space_pass.cpp
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system-tests-a5sim cascade (PR-caused):
- test(st/matmul_mx): test_matmul_mx_compiles_ptoas called bare
matmul_mx_prequant.compile() with no config, so platform=None defaulted
the backend to Ascend910B. set_backend_type is only ever called from
ir.compile(), so this was the sole 910B source in the a5sim session and
cascaded ("already set to Ascend910B, cannot change to Ascend950") across
every sibling a5sim test. Compile with config=test_config (platform=a5sim
-> Ascend950) instead, matching every other a5sim test, and drop the
manual set_backend_type/reset_for_testing poking.
matmul_mx_acc in-place accumulation (Codex review, P2):
- codegen(matmul_mx_acc): route through make_acc_codegen (in-place lowering)
like matmul_acc/gemv_acc. The op carries set_output_reuses_input(0), so
the generic N-ary lowering (MakeNaryCodegenPTO) wrongly emitted the
accumulator and output as separate buffers, violating ptoas's ins(acc)
== outs() requirement. Generalize make_acc_codegen to variable arity
(first IR arg is the in-place accumulator; the rest are operands) so it
covers both 3-arg (acc, lhs, rhs) and 5-arg MX shapes. Add a codegen
regression test asserting ins(acc) == outs.
dtype predicate coverage (CodeRabbit out-of-diff):
- test(dtype): cover DT_FP8E8M0 in is_int and the type-predicate
mutual-exclusion list so a regression reporting it as both float and int
cannot pass silently.
dist-system-tests is skipped: it fails on the latest main (InsertCommFence
commit) too, so it is pre-existing and out of scope for this PR.
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Adds the MX block-scale matmul family: tile.matmul_mx / matmul_mx_acc (in-place accumulation) / matmul_mx_bias, with 2D tile shape guards and FP8E8M0 scale checks. Codegen: make_acc_codegen is generalized to variable arity so matmul_mx_acc lowers in place (ptoas c_in == dst), and PTOCodegen hoists the Acc alloc_tile to the function prologue (prologue-safe physical extents) to fix the split-K Acc SSA domination, plus the Acc if-phi canonical-SSA resolution. expand_mixed_kernel_pass stages MX activation scales across AIC/AIV cores so tquant→matmul_mx mixed kernels sync correctly. Removes the now-obsolete kUnregisteredCubeOps workaround in the infer-memory-space pass. Adds the a5sim compile-through-ptoas ST and wires it into CI. Phase 4 of the hw-native-sys#2117 split. Closes hw-native-sys#1975.
Introduce DataType::FP8E8M0 (1-byte E8M0 MX scale exponent) through the dtype system, EmitC/MLIR spellings (float8_e8m0_t / !pto.f8E8M0), and Python bindings/stubs/DSL resolver/JIT torch maps. Also fills previously missing EmitC/MLIR mappings for FP8E4M3FN, FP8E5M2, and packed FP4. No new memory spaces or ops. Phase 1.1 of the hw-native-sys#2117 split. Refs hw-native-sys#1975.
Add Ascend950 LeftScale/RightScale memory spaces (L0A/L0B MX scale buffers, SoC capacity, loc=scaling) and the scale data path: tile.load mx_layout, Mat↔Scale move with target_shape and deferred fill until tget_scale_addr, FP4/FP8E8M0 reinterpret_view aliases, and ptoas ND-flat → mx_a_zz preprocess. No MX quant/matmul ops yet. Phase 2 of the hw-native-sys#2117 split (includes former Phase 1.2). Depends on FP8E8M0 (hw-native-sys#2144). Refs hw-native-sys#1975. Interface alignment (memspace + scale data path): pto-isa (A5 / MX): TileType::ScaleLeft / ScaleRight — L0A/L0B MX scale buffers (include/pto/common/type.hpp); payload float8_e8m0_t Layout::MX_A_ZZ / MX_A_ND / MX_A_DN — activation scale GM layouts; TLoadMxCube* (AZZ2ZZ / AND2ZZ / …); SFractal=32 row-major ZZ Layout::MX_B_NN / MX_B_ND / MX_B_DN — weight scale layouts; col-major NN for MX_B_* TMov CommonCheckMX — uint8_t Mat → float8_e8m0 ScaleLeft/Right GetScaleAddr(Left/Right) — bind Scale tile to L0 sidecar before fill (sidecar bind-then-fill; Mat→Mat tmov illegal on A5) PTOAS (v0.48+ dialect / EmitC): loc=scaling + !pto.f8E8M0 → TileType::ScaleLeft|ScaleRight (ui8 + scaling wrongly maps to Fixpipe TileType::Scaling; LeftScale/RightScale share one MLIR loc `scaling` until distinct) #pto.layout<mx_a_zz|mx_a_nd|…|mx_b_nn|…> on make_tensor_view / tload → Layout::MX_*; InferPTOLayout prefers mx_a_zz/mx_b_nn for !pto.f8E8M0 Mat+fractal=32 pto.tmov Mat→scaling — must follow tget_scale_addr (matches PTOA5NormalizeTMovPass); PyPTO defers fill until then EmitC preprocess: float8_e8m0/uint8 MX_A_ZZ → MX_A_ND so TLoad uses AND2ZZ (activation scales are ND-flat on GM); MTE3 drain before Vec TPUSH; pipe_barrier before MX_A_ND TLOAD after AIV store PyPTO ↔ interface: MemorySpace::LeftScale ↔ loc=scaling + !pto.f8E8M0 ↔ ScaleLeft MemorySpace::RightScale ↔ loc=scaling + !pto.f8E8M0 ↔ ScaleRight tile.load(..., mx_layout=mx_a_zz|…) ↔ #pto.layout<…> ↔ Layout::MX_* tile.move Mat→LeftScale/RightScale ↔ deferred tmov after GetScaleAddr FP8E8M0 / UINT8 scale payload ↔ float8_e8m0_t (1-byte MX exp) Dependencies: - PyPTO: FP8E8M0 dtype (hw-native-sys#2144 / DataType::FP8E8M0) - PTOAS: v0.48+ (loc=scaling, MX layouts, NormalizeTMov) - pto-isa: A5 MX TileType + Layout + TLoadMx / TMov / GetScaleAddr Also includes review/CI fixes for hw-native-sys#2147: - Scope tile.reshape layout inheritance to MX scale fractal=32 only - Stamp memory_space_ on tile.move only for LeftScale/RightScale - FIFO-sticky: registered tpush_to_*/tpop_from_* + Scale moves only - Drop drive-by Bias from IsCubeMemorySpace; do not change .gitignore - Default mx_layout loads to Mat; tighten mx_layout / flat-store checks - Ascend950 LeftScale/RightScale capacity and Mat→Scale path UTs
Add Ascend950 LeftScale/RightScale memory spaces (L0A/L0B MX scale buffers, SoC capacity, loc=scaling) and the scale data path: tile.load mx_layout, Mat↔Scale move with target_shape and deferred fill until tget_scale_addr, FP4/FP8E8M0 reinterpret_view aliases, and ptoas ND-flat → mx_a_zz preprocess. No MX quant/matmul ops yet. Phase 2 of the hw-native-sys#2117 split (includes former Phase 1.2). Depends on FP8E8M0 (hw-native-sys#2144). Refs hw-native-sys#1975. Also includes review fixes for hw-native-sys#2147: - Drop unused TakePending*/DeferTFree/TakeDeferredTFreeCount (flush API already lives in feat/mx-quant-ops and feat/mx-matmul-ops) - Assert no unflushed deferred scale fills at GenerateFunction end - Use INTERNAL_UNREACHABLE_SPAN for the unsupported f8 Mat→Scale path - Align _barrier_before_mx_a_nd_tload comment with no-distance-cutoff code Co-authored-by: Cursor <cursoragent@cursor.com>
Add Ascend950 LeftScale/RightScale memory spaces (L0A/L0B MX scale buffers, SoC capacity, loc=scaling) and the scale data path: tile.load mx_layout, Mat↔Scale move with target_shape and deferred fill until tget_scale_addr, FP4/FP8E8M0 reinterpret_view aliases, and ptoas ND-flat → mx_a_zz preprocess. No MX quant/matmul ops yet. Phase 2 of the hw-native-sys#2117 split (includes former Phase 1.2). Depends on FP8E8M0 (hw-native-sys#2144). Refs hw-native-sys#1975. Also includes review/CI fixes for hw-native-sys#2147: - Drop unused TakePending*/DeferTFree/TakeDeferredTFreeCount (flush API already lives in feat/mx-quant-ops and feat/mx-matmul-ops) - Assert no unflushed deferred scale fills at GenerateFunction end - Use INTERNAL_UNREACHABLE_SPAN for the unsupported f8 Mat→Scale path - Align _barrier_before_mx_a_nd_tload comment with no-distance-cutoff code - Narrow TileType.shape dims via isinstance(ConstInt) for pyright Co-authored-by: Cursor <cursoragent@cursor.com>
Add Ascend950 LeftScale/RightScale memory spaces (L0A/L0B MX scale buffers, SoC capacity, loc=scaling) and the scale data path: tile.load mx_layout, Mat↔Scale move with target_shape and deferred fill until tget_scale_addr, FP4/FP8E8M0 reinterpret_view aliases, and ptoas ND-flat → mx_a_zz preprocess. No MX quant/matmul ops yet. Phase 2 of the hw-native-sys#2117 split (includes former Phase 1.2). Depends on FP8E8M0 (hw-native-sys#2144). Refs hw-native-sys#1975. Also includes review/CI fixes for hw-native-sys#2147: - Drop unused TakePending*/DeferTFree/TakeDeferredTFreeCount (flush API already lives in feat/mx-quant-ops and feat/mx-matmul-ops) - Assert no unflushed deferred scale fills at GenerateFunction end - Use INTERNAL_UNREACHABLE_SPAN for the unsupported f8 Mat→Scale path - Align _barrier_before_mx_a_nd_tload comment with no-distance-cutoff code - Narrow TileType.shape dims via isinstance(ConstInt) for pyright
Adds the MX quantization op family in a new src/ir/op/tile_ops/mx.cpp:
tile.tquant / mx_quant (block-32 dynamic quant: FP16/FP32/BF16 →
{quantized bytes, e8m0 scale}, mode selects mxfp8_e4m3/e5m2/mxfp4_e2m1,
K must divide 32), tile.tdequant (integer per-row dequant), and
tile.tget_scale_addr (bind a Scale tile to GetScaleAddr and flush the
PR2 deferred Mat→Scale fill). The lower_composite pass rewrites the
1-arg DSL tquant into the 3-arg DPS form (materializing FP32 scratch);
datamove codegen emits pto.tquant.mx / pto.tdequant. PTOCodegen gains
MakeTuple/TupleGetItemExpr resolution for the multi-output tquant.
Phase 3 of the hw-native-sys#2117 split. Refs hw-native-sys#1975.
Adds the MX block-scale matmul family: tile.matmul_mx / matmul_mx_acc (in-place accumulation) / matmul_mx_bias, with 2D tile shape guards and FP8E8M0 scale checks. Codegen: make_acc_codegen is generalized to variable arity so matmul_mx_acc lowers in place (ptoas c_in == dst), and PTOCodegen hoists the Acc alloc_tile to the function prologue (prologue-safe physical extents) to fix the split-K Acc SSA domination, plus the Acc if-phi canonical-SSA resolution. expand_mixed_kernel_pass stages MX activation scales across AIC/AIV cores so tquant→matmul_mx mixed kernels sync correctly. Removes the now-obsolete kUnregisteredCubeOps workaround in the infer-memory-space pass. Adds the a5sim compile-through-ptoas ST and wires it into CI. Phase 4 of the hw-native-sys#2117 split. Closes hw-native-sys#1975. Co-authored-by: Cursor <cursoragent@cursor.com>
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Add Ascend950 LeftScale/RightScale memory spaces (L0A/L0B MX scale buffers, SoC capacity, loc=scaling) and the scale data path: tile.load mx_layout, Mat↔Scale move with target_shape and deferred fill until tget_scale_addr, FP4/FP8E8M0 reinterpret_view aliases, and ptoas ND-flat → mx_a_zz preprocess. No MX quant/matmul ops yet. Phase 2 of the hw-native-sys#2117 split (includes former Phase 1.2). Depends on FP8E8M0 (hw-native-sys#2144). Refs hw-native-sys#1975. Also includes review/CI fixes for hw-native-sys#2147: - Drop unused TakePending*/DeferTFree/TakeDeferredTFreeCount (flush API already lives in feat/mx-quant-ops and feat/mx-matmul-ops) - Assert no unflushed deferred scale fills at GenerateFunction end - Use INTERNAL_UNREACHABLE_SPAN for the unsupported f8 Mat→Scale path - Align _barrier_before_mx_a_nd_tload comment with no-distance-cutoff code - Narrow TileType.shape dims via isinstance(ConstInt) for pyright after rewrite; raise if PTOAS changed its layout spelling. count equals expected Vec-TPUSH count.
Add Ascend950 LeftScale/RightScale memory spaces (L0A/L0B MX scale buffers, SoC capacity, loc=scaling) and the scale data path: tile.load mx_layout, Mat↔Scale move with target_shape and deferred fill until tget_scale_addr, and FP8E8M0 reinterpret_view aliases. Reject FP8E5M2 reinterpret on Ascend950. No MX quant/matmul ops or MXFP4 aliases yet (those land in hw-native-sys#2117 with ND rewrite / AIC PIPE_ALL barriers). Phase 2 of the hw-native-sys#2117 split (includes former Phase 1.2). Depends on FP8E8M0 (hw-native-sys#2144). Refs hw-native-sys#1975. Also includes review/CI fixes for hw-native-sys#2147: - Drop unused TakePending*/DeferTFree/TakeDeferredTFreeCount (flush API already lives in feat/mx-quant-ops and feat/mx-matmul-ops) - Assert no unflushed deferred scale fills at GenerateFunction end - Use INTERNAL_UNREACHABLE_SPAN for the unsupported f8 Mat→Scale path - Narrow TileType.shape dims via isinstance(ConstInt) for pyright - Drop fragile PTOAS C++ regex post-process (MX_A_ZZ→ND, MTE3 drain, pipe_barrier); defer sync/layout fixes to hw-native-sys#2117
Adds the MX quantization op family in a new src/ir/op/tile_ops/mx.cpp:
tile.tquant / mx_quant (block-32 dynamic quant: FP16/FP32/BF16 →
{quantized bytes, e8m0 scale}, mode selects mxfp8_e4m3/e5m2/mxfp4_e2m1,
K must divide 32), tile.tdequant (integer per-row dequant), and
tile.tget_scale_addr (bind a Scale tile to GetScaleAddr and flush the
PR2 deferred Mat→Scale fill). The lower_composite pass rewrites the
1-arg DSL tquant into the 3-arg DPS form (materializing FP32 scratch);
datamove codegen emits pto.tquant.mx / pto.tdequant. PTOCodegen gains
MakeTuple/TupleGetItemExpr resolution for the multi-output tquant.
Phase 3 of the hw-native-sys#2117 split. Refs hw-native-sys#1975.
Adds the MX block-scale matmul family: tile.matmul_mx / matmul_mx_acc (in-place accumulation) / matmul_mx_bias, with 2D tile shape guards and FP8E8M0 scale checks. Codegen: make_acc_codegen is generalized to variable arity so matmul_mx_acc lowers in place (ptoas c_in == dst), and PTOCodegen hoists the Acc alloc_tile to the function prologue (prologue-safe physical extents) to fix the split-K Acc SSA domination, plus the Acc if-phi canonical-SSA resolution. expand_mixed_kernel_pass stages MX activation scales across AIC/AIV cores so tquant→matmul_mx mixed kernels sync correctly. Removes the now-obsolete kUnregisteredCubeOps workaround in the infer-memory-space pass. Adds the a5sim compile-through-ptoas ST and wires it into CI. Phase 4 of the hw-native-sys#2117 split. Closes hw-native-sys#1975. Co-authored-by: Cursor <cursoragent@cursor.com>
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Add Ascend950 LeftScale/RightScale memory spaces and the scale data path (tile.load mx_layout, Mat→Scale move with deferred fill), plus tile.tget_scale_addr (flush PendingScaleFill) and tile.matmul_mx only (pto.tmatmul.mx). Host-prequant FP8E4M3FN data + FP8E8M0 scales; reject FP8E5M2 for reinterpret and matmul_mx data dtype. Document pto-isa and PTOAS constraints in operators docs (en/zh). Defer to hw-native-sys#2117: tquant/tdequant, MXFP4, matmul_mx_acc/bias, ND rewrite / AIC PIPE_ALL, ExpandMixed FIFO sticky. Depends on FP8E8M0 (hw-native-sys#2144). Refs hw-native-sys#1975.
Adds the MX quantization op family in a new src/ir/op/tile_ops/mx.cpp:
tile.tquant / mx_quant (block-32 dynamic quant: FP16/FP32/BF16 →
{quantized bytes, e8m0 scale}, mode selects mxfp8_e4m3/e5m2/mxfp4_e2m1,
K must divide 32), tile.tdequant (integer per-row dequant), and
tile.tget_scale_addr (bind a Scale tile to GetScaleAddr and flush the
PR2 deferred Mat→Scale fill). The lower_composite pass rewrites the
1-arg DSL tquant into the 3-arg DPS form (materializing FP32 scratch);
datamove codegen emits pto.tquant.mx / pto.tdequant. PTOCodegen gains
MakeTuple/TupleGetItemExpr resolution for the multi-output tquant.
Phase 3 of the hw-native-sys#2117 split. Refs hw-native-sys#1975.
Adds the MX block-scale matmul family: tile.matmul_mx / matmul_mx_acc (in-place accumulation) / matmul_mx_bias, with 2D tile shape guards and FP8E8M0 scale checks. Codegen: make_acc_codegen is generalized to variable arity so matmul_mx_acc lowers in place (ptoas c_in == dst), and PTOCodegen hoists the Acc alloc_tile to the function prologue (prologue-safe physical extents) to fix the split-K Acc SSA domination, plus the Acc if-phi canonical-SSA resolution. expand_mixed_kernel_pass stages MX activation scales across AIC/AIV cores so tquant→matmul_mx mixed kernels sync correctly. Removes the now-obsolete kUnregisteredCubeOps workaround in the infer-memory-space pass. Adds the a5sim compile-through-ptoas ST and wires it into CI. Phase 4 of the hw-native-sys#2117 split. Closes hw-native-sys#1975.
Restore EmitC MX_A_ZZ→MX_A_ND rewrite and emit PIPE_ALL immediately before mx_a_* tload / after e8m0 tpop so AIV GM store → AIC AND2ZZ visibility survives --enable-insert-sync. Keep post-EmitC regex as a belt-and-suspenders fallback. Restore deferred Mat→Scale fill / per-core tfree drain APIs needed by the MX quant path. Omit producer TPUSH pipe_barrier+dsb (not a hard board dependency once AIC barriers are present).
When M*K>1024 and M*K%256==0, pto-isa StoreScalingUnrolled writes 2×groups floats. Size both max and scaling to [1, 2*groups] so overflow does not clobber adjacent e8m0 and the planner keeps max↔exp co-placement.
Treat FP4 tile shape/valid_shape as packed storage units (K/2) while scale groups and matmul K-matching use logical element counts. Re-allow INT8↔FP4 reinterpret_view aliases for MXFP4 paths (kept out of hw-native-sys#2147).
…-sys#2117 Re-introduce V2C/scale FIFO sticky (moved out of hw-native-sys#2147), dedupe TakePending helpers after rebase, allow FP4/INT8 matmul_mx data while still rejecting FP8E5M2, and document hw-native-sys#2117 ISA/PTOAS extension constraints (en/zh).
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Summary
Depends on #2147 (minimal host-prequant MXFP8 matmul baseline).
This PR stacks on #2147 and adds:
tile.tquant/tdequant(+ lower_composite 2× scratch)tile.matmul_mx_acc/matmul_mx_biasMX_A_ZZ→MX_A_ND) + AICPIPE_ALLbeforemx_a_*tloadStill rejects FP8E5M2 for MX data (same as #2147); allows
FP8E4M3FN/FP4/ tquantINT8.Docs: operators MX constraints — #2147 baseline tables + #2117 extension tables (en/zh).
ISA / PTOAS extensions (on top of #2147)
tquantscratchPIPE_ALL(not TPUSH+dsb)Test plan
test_mx_ops/test_mx_ops_codegen/test_mx_scale_memspacetest_matmul_mx,test_tquanton a5/a5simCo-authored-byon tip commits