Revert PR-1d: CudaRenderCtx was the same anti-pattern reskinned#82
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Replaces § 3.2.1 ("Split LoweringCtx from CudaRenderCtx") with
"Dissolve LoweringCtx (no-context principle)". Adds a sub-clause
to § 1 (ACID test) codifying the three-bucket discipline:
1. Cross-pass data → typed IR op
2. Intra-pass scratch → function-local / explicit kwarg
3. Services → immutable Services handle
Adds amendment-log entry § 10.2. Refers forward to discipline rule
D22 (strict monotonic decrease of ctx-field count; to be codified
in code_discipline.md per the standard cadence).
Triggered by user review of merged PR-1d (#81) which introduced
CudaRenderCtx with 10 fixed-schema fields — the same anti-pattern
the redesign is supposed to eliminate. PR-1d reverted in #82.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
StarGazerM
added a commit
that referenced
this pull request
May 20, 2026
Replaces § 3.2.1 ("Split LoweringCtx from CudaRenderCtx") with
"Dissolve LoweringCtx (no-context principle)". Adds a sub-clause
to § 1 (ACID test) codifying the three-bucket discipline:
1. Cross-pass data → typed IR op
2. Intra-pass scratch → function-local / explicit kwarg
3. Services → immutable Services handle
Adds amendment-log entry § 10.2. Refers forward to discipline rule
D22 (strict monotonic decrease of ctx-field count; to be codified
in code_discipline.md per the standard cadence).
Triggered by user review of merged PR-1d (#81) which introduced
CudaRenderCtx with 10 fixed-schema fields — the same anti-pattern
the redesign is supposed to eliminate. PR-1d reverted in #82.
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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Why revert
PR-1d (#81) moved 10 CUDA-render-private fields from
LoweringCtxinto a newCudaRenderCtxdataclass. The shape is the anti-pattern — a fixed-schema attribute carrier where adding any new CUDA render feature (a new tile mode, a new gate, a new ballot variant) requires editinglower_ctx.pyto add a field.This is the same shape as the original bool-field anti-pattern (
ep.work_stealing/ep.dedup_hash/ep.bg_enabled) that A3-1/2/3 already removed, and the same shape as the runner monolith that Phase R targets. We just moved the problem from one named carrier to another.Per the user: it's a clear ACID-test violation (spec § 1).
What needs to change
Spec amendment 2 (separate PR) replaces "split LoweringCtx → CudaRenderCtx" (§ 3.2.1) with a no-context principle:
view_specs,iir, name maps that pass A sets and pass B reads): becomes IR ops. Information flows only via the IR.valid_vars threaded into one render call): becomes function-local state, no ctx parameter.compiler,name_gen,plugin_registry): explicit kwargs or aServiceshandle that is never mutated.After the rewrite,
LoweringCtx,CudaRenderCtx,KernelCtx,InitialProgall dissolve.What stays / what comes back
ctx.<extracted_field>go back to reading fromLoweringCtx(this revert), and will dissolve entirely in the redesigned PR-1d.targetthreading viaInitialProg.target/KernelCtx.targetlikely also needs rework under the same principle — out of scope for this revert; we'll handle in the re-plan.Test plan
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