PR-1: foundation — CudaRenderCtx + target parametricity + plugin-group split (Wave T1 + B2-1)#76
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…2-1)
Per docs/phase_decomposition_redesign.md § 6.1: establishes the
target-abstraction surface every subsequent migration PR builds on.
Zero target migration in scope — CUDA remains the byte-equivalence
anchor; 535 byte-eq goldens stay green.
Changes:
1. CudaRenderCtx (NEW src/srdatalog/ir/codegen/cuda/lower_ctx.py).
11 CUDA-render-side identifier fields move off the dialect
`LoweringCtx` into a target-private companion class. The dialect
`LoweringCtx` now threads `render_ctx: CudaRenderCtx` and exposes
the 11 fields as forwarding properties — every legacy read site
(`ctx.view_var_names`, `ctx.output_var`, …) keeps working; new
code prefers the explicit `ctx.render_ctx.<field>` form.
2. Pragma-scratch flag flips become function-local kwargs. The 4
wrap-op lowerings (lower_dedup_gate, lower_ws_scope,
lower_block_group_root, lower_tiled_cartesian_in_chain) stop
mutating `ctx.<flag>` for the duration of the call. The inner
helpers (`_lower_insert_into`, the BG/tiled dispatchers) either
accept new kwargs (`is_dedup_gate`, `is_ws_scope`) or are called
directly without flag flips (BG/tiled — the helpers themselves
ARE the dispatched variants). 4 ctx-flip patterns removed
total. Legacy `ep.<flag>: bool` paths still set the ctx field
via `LowerKernelBodyShim`, so the dual-write transition stays
byte-equivalent.
3. Compiler.run(target='cuda') kwarg threaded through KernelCtx /
InitialProg `target` fields. The dataclass-aware Compiler.run
coerces `prog.target` to the kwarg value before pipeline runs.
VerifyRenderabilityShim + RenderShim consult `state.target`
instead of the literal 'cuda'.
4. Shim renames: `LowerScanPipelineShim` -> `LowerKernelBodyShim`;
`CudaRenderShim` -> `RenderShim`. Pipeline names update
correspondingly (lower_scan_pipeline -> lower_kernel_body;
cuda_render -> render). Back-compat aliases keep external
pinned references importing the same class.
5. Plugin entry-point group split (pyproject + core/plugin.py):
`srdatalog.plugins` (legacy) split into `srdatalog.dialects`
(data dialects) + `srdatalog.targets` (render targets). The 6
built-in dialects move to the new group; legacy group is still
walked with `DeprecationWarning` for one release cycle so
external plugins (e.g. jaccard demo) keep working unmodified.
`Compiler.with_default_plugins()` walks all three groups by
default.
Tests:
- tests/test_cuda_render_ctx.py — construction + threading +
legacy-kwargs compat (8 tests).
- tests/test_compiler_run_target_kwarg.py — target kwarg
propagation + unknown-target failure (11 tests).
- tests/test_plugin_group_split.py — three-group discovery +
DeprecationWarning + back-compat (8 tests).
- tests/test_discipline_lower_ctx_pinned.py extended — pins
CudaRenderCtx field count + dialect ctx render_ctx slot.
Quality gates:
- 535 byte-eq tests green (test_runner_byte_equivalence +
test_byte_equivalence_jit + test_cuda_complete_runner +
test_dedup_hash_byte_equivalence).
- All pragma e2e tests green (93 tests).
- All lowering byte-eq tests green (excluding pre-existing
jaccard install failures).
- Full suite: 1635 passed (was 1603 baseline, +32 new tests);
same 32 pre-existing failures (all from local jaccard install
where `srdatalog_jaccard:register` module has no `register`).
- mypy clean on touched files.
- `ruff check` + `ruff format --check` clean.
- D10 + D19 discipline tests green.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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Summary
First PR of the unified decomposition redesign (per
docs/phase_decomposition_redesign.md). Foundation work that enables PR-2 through PR-6.What lands
CudaRenderCtx(11 fields, target-private) — extracted fromLoweringCtxper spec § 3.2.1LoweringCtxslimmed: 11 CUDA-render fields become forwarding properties torender_ctx; frameworkLowerCtxstays at 5 fields (D10-pinned)lower_dedup_gate+lower_ws_scopepassis_dedup_gate=True/is_ws_scope=Trueto_lower_insert_intoinstead of mutating ctxCompiler.run(prog, pipeline=..., target='cuda')target kwargKernelCtx.target+InitialProg.targetfields threaded throughCudaRenderShim→RenderShim,LowerScanPipelineShim→LowerKernelBodyShimsrdatalog.plugins→srdatalog.dialects+srdatalog.targets; legacy group walked withDeprecationWarningfor back-compat (jaccard demo plugin verified still loads)CudaRenderCtx final field list (11 fields — 2 more than spec preview)
view_var_names,output_var,output_var_overrides,view_slot_bases,rel_index_types,tiled_cartesian_valid_var,ws_cartesian_valid_var,ws_cartesian_bound_vars,neg_pre_narrow,dedup_hash_vars,debug. The 2 additions (dedup_hash_vars,debug) are pervasive CUDA identifier scratch on the legacy ctx that fit the target-private bucket.Surprising findings (per agent's audit)
is_countingis NOT a pragma scratch flag in practice — it's a phase-mode flag set once by the shim from external runner kwarg. Kept onLoweringCtxrather than threading through every helper (no byte-eq benefit; large change). Spec § 3.2.1's listing was slightly inaccurate._lower_root_cj_bg/_lower_nested_cart_tiledARE the dispatch variants — they don't read a flag, they ARE the variant code. So the wrap-op lowerings just call them directly; no kwarg needed.render_ctxlives on dialect-levelLoweringCtxonly (not frameworkLowerCtx— that stays at 5 fields per the explicit "DO NOT add fields" constraint). Resolves the internal contradiction in my task prompt (which said both "activate test asserting 6 fields" and "DO NOT add fields").__slots__on dialectLoweringCtx— production fixtures dynamicallysetattr(ctx, 'rest_for_bg_root', rest); slot-pinning would break the BG test path.srdatalog.targetsentries yet — CUDA target stays wired via dialect registrations for now; later PRs addsrdatalog.codegen.cuda:registerunder the new group.Test plan
test_runner_byte_equivalence(276+2 skip) +test_byte_equivalence_jit(253) +test_cuda_complete_runner+test_dedup_hash_byte_equivalence— all greenrender_ctx;CudaRenderCtxat 11 fields). FrameworkLowerCtxstill at 5What this unblocks
PR-2a (RIR framework + structural/scheduling/kernel-body/dedup lowerings) — agent will branch off this PR's commit once merged.
🤖 Generated with Claude Code