xilinx: add out-of-context place-and-route support

[nkapreTT]

Add support for out-of-context (OOC) placement and routing in the
Xilinx flow by bypassing automatic IO buffer insertion. This is
needed when a sub-module's top-level port count exceeds the target
device's physical IO pin count -- placement would otherwise fail
during buffer insertion.

Two flags accepted, identical effect: --no-iobs (terser) and
--out-of-context (aligned with the existing OOC nomenclature used
by nextpnr-ecp5 and Vivado).

Changes:

• xilinx/main.cc -- register --out-of-context as an alias of
  --no-iobs. When either is passed, set ctx->settings for both
  disable_iobs AND arch.ooc.

  The arch.ooc setting is the load-bearing piece: without it,
  common/kernel/timing.cc populates ooc_port_nets as an empty set
  and the topological-order seeding loop (guarded by arch.ooc)
  never enqueues top-level input ports. Result: every
  combinational path starting at an unbuffered input is silently
  dropped from the timing report -- you get an Fmax estimate that
  ignores roughly half the design. Matches the OOC pattern
  nextpnr-ecp5 already uses.

• xilinx/pack.cc -- factor the two duplicated $nextpnr_*buf
  cleanup blocks (one in the xc7 packer path, one in the
  ultrascale+ path) into a single static helper
  remove_nextpnr_iobs(). Inside the helper, also erase the
  cleaned-up cells from ctx->port_cells. Without that erase, the
  raw pointers held by ctx->port_cells became dangling the moment
  the owning unique_ptrs in ctx->cells were destroyed, and any
  later pass that queried port_cells (e.g. XDC constraint
  handling, timing analysis post-pack) could crash on a freed
  pointer.

Validated locally on a sub-module design with ~700 top-level ports
on xc7a200t: design now packs, places, and reports a populated
timing report with paths sourced from top-level inputs.