xilinx: fix SRLC32E Q31 cascade and add WE consistency check

[nkapreTT]

Two cascaded SRLC32E primitives currently fail routing in
nextpnr-xilinx because the packer never xforms the source-cell
Q31 port to its bel-level cascade pin MC31. The chipdb already
exposes MC31 on SLICE_LUTX and the corresponding DOUTMUX:MC31 site
pip, so the gap was purely on the packer side. This patch wires
Q31 -> MC31 into pack_srls() so Yosys-emitted SRLC32E chains route
cleanly under both router1 and router2.

While here, also add a WE net consistency check in
xc7_logic_tile_valid()'s half-tile loop. The WEMUX driving the
SRL/DRAM WE pin is shared across the bottom half of a SLICEM, so
two SRLs from independent write-enable domains cannot legally share
a half-SLICE. Today the placer happily places them together and
the router then fails on SITEWIRE/SLICE_*/WEMUX_OUT. Mirror the
existing wclk check by storing the WE net on lutInfo in
assignCellInfo() and asserting agreement inside the half-tile loop.

A minimal two-SRL repro (one SRLC32E driving another via Q31->D)
now routes under both routers; previously it errored out with
"No wire found for port Q31 on source cell".