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feat(k8s): add multimodal Dynamo RL validation - #1

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qiwa/dgd-basefrom
qiwa/dynamo-k8s-mm-test
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feat(k8s): add multimodal Dynamo RL validation#1
furionw wants to merge 35 commits into
qiwa/dgd-basefrom
qiwa/dynamo-k8s-mm-test

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@furionw

@furionw furionw commented Jul 9, 2026

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Based on PrimeIntellect-ai/prime-rl#2965.

Why

Prime's native Dynamo backend needs repeatable ARM Kubernetes validation for multimodal rollouts, cross-node trainer handoff, and weight synchronization. Manual runs can reuse stale PVC batches or lose selected GPUs before deployment. This workflow isolates every stage's outputs and deploys the real GPU-requesting pods immediately after just-in-time node selection.

What Change

  • Add a digest-pinned, shared-PVC multimodal Kubernetes workflow.
  • Add one-step Qwen3-VL-2B and Qwen3.5-2B validation stages plus the longer Qwen3-VL-4B learning stage.
  • Use the model-specific qwen3-vl and qwen3.5 renderers so image inputs become vision tokens and training tensors.
  • Configure Qwen3.5's required Mamba/NIXL state layout.
  • Harden model caching, scheduling, output isolation, and completion checks.

Test Plan

  • ARM overlay tests: Dynamo 25 passed; Prime 32 passed, 5 skipped.
  • CPU image-render precheck: Qwen3-VL-2B and Qwen3.5-2B both produced image tensors.
  • ./run.sh smoke: 16 three-turn image rollouts, 0% errors/truncation; trainer step completed at 256 tokens/s and 18.1 GiB peak memory; orchestrator/trainer exited 0.
  • ./run.sh qwen35: 16 three-turn image rollouts, 0% errors and 6.2% truncation; trainer step completed at 222 tokens/s and 20.2 GiB peak memory; orchestrator/trainer exited 0.

Both one-step gates had reward 0 and 0/16 trainable samples; they validate the multimodal RL execution path, not model quality or learning convergence.

furionw added 30 commits July 9, 2026 14:30
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
furionw added 5 commits July 9, 2026 17:34
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
Signed-off-by: furionw <qiwa@nvidia.com>
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