Cache simulator

In this project, we extended a timing simulator (written in C) to model instruction/data caches; then we used the timing simulator to perform architectural exploration and study cache behavior under different configurations.

Information

• Course: Advanced Computer Architectures
• Academic Year: 2025/2026
• Date: July 2026
• Authors:
  • Giacomo Maglio - 10858201
  • Francesca Morciano - 10900578

Repository Structure

Cache_Simulator/
├── sweep/      # implementation of a parameters sweeper
|   ├── inputs/  # both provided and personalized test
|   ├── src/
|   ├── sweep_results/  # raw .csv files, contain results on performed sweeps
|   ├── Makefile
|   └── README.md   # sweeper use instructions
├── task_1/     # source code for our cache implementations
|   ├── inputs/ # both provided and personalized test
|   ├── src/
|   ├── Makefile
|   └── run.py
├── task_2/     # source code for our most performant cache design
|   ├── most_performant.design/
|   |   ├── inputs/ # both provided and personalized test
|   |   ├── src/
|   |   ├── Makefile
|   |   └── run.py
|   └── Cache_Simulator_report.pdf  # project report
└── README.md

Running the Project

Brief instructions on how to run the project.

Inside the chosen implementation folder:

make sim # to build the simulator executable
make run sim # to run sim compared with basesim on all inputs

Note: to run code inside sweep/, refer to the README.md in that folder.