Pinned Loading

1. internet_clock internet_clock Public

   A digital 7-segment clock, synced via internet.

2. weather_station_sensor weather_station_sensor Public

   Weather Station Sensor

3. riscv_cpu riscv_cpu Public

   My Attempt at writing a simple RISC-V CPU in Verilog.

   Verilog 2

4. audio_amplifier audio_amplifier Public

   Audio pre- and poweramplifier, supplies

5. signal_probe signal_probe Public

   Acquiring analog data via adc, transfer with dma, process, write to dac on a samd51.

   C++

6. fftodile fftodile Public

   Forked from pulp-platform/croc

   A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

   SystemVerilog