Popular repositories Loading

1. Torus-Systolic-array-HDL Torus-Systolic-array-HDL Public

   Verilog implementation of a Torus-based systolic array accelerator for matrix multiplication.

   Verilog 4

2. FashionMnist_LeNet5 FashionMnist_LeNet5 Public

   SystemVerilog FPGA acceleration of LeNet-5 CNN for Fashion-MNIST classification, powered by a 5x5 2D Torus Systolic Array with bit-exact Python simulator, and out-of-context Vivado synthesis benchm…

   SystemVerilog 4

3. DFT-BIST-Convolver-Architecture DFT-BIST-Convolver-Architecture Public

   Built-In Self-Test (BIST) & DFT architectures (STUMPS vs. RTS) in Verilog HDL for a 2D pipelined CNN convolution engine, achieving 100% fault coverage.

   Verilog 1