PMU: phytium: update phytium PMUcontroller driver support to 6.6.0.4#1676
PMU: phytium: update phytium PMUcontroller driver support to 6.6.0.4#1676zhangfuxiang123 wants to merge 18 commits intodeepin-community:linux-6.6.yfrom
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…CIe PMU. This reverts commit c019dd510742274e7faadf2ccf934902638c7199. Reason for revert: <Modify the HID for PS240XX PCIe PMU> Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Hu Xianghua <huxianghua@phytium.com.cn>
…DR PMU. This reverts commit 6b95559ae805afcc01cd1960da56c96214ef3522. Reason for revert: <Modify the HID for PS240XX DDR PMU> Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Hu Xianghua <huxianghua@phytium.com.cn>
Add a new HID to differentiate between PS230XX and PS240XX DDR PMU and add support for PS240XX platforms. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Hu Xianghua <huxianghua@phytium.com.cn>
Add a new HID to differentiate between PS230XX and PS240XX PCIe PMU and add support for PS240XX platforms. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Add DDR controller performance monitoring unit (PMU) Support for Phytium PD2408 SoCs. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Add a prefix before the name of the pd2408 dmu pmu cycles event. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Add a prefix before the name of the ddr pmu cycles event. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Add a prefix before the name of the pcie pmu cycles event. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Fix a system panic issue caused by the PS23X00 DDR PMU on Phytium PBF firmware version below 1.20. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
When the dmu pmu driver is migrated to the target cpu, offlining the target cpu will cause the system panic. We fix this issue. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Standarize event naming to use all lowercase and avoid mixing uppercase mixing uppercase and lowercase letters. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Introduce driver support for the PCIe PMU v2p0. The driver enables discovery and registration of PMU capabilities in PCIe devices. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Introduce a unified driver support for the DDR performance monitoring unit. The driver enables discovery and registration of PMU capabilities in DDR devices. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Introduce driver support for the PCIe Link performance monitoring unit. The driver enables discovery and registration of PMU capabilities in PCIe Link devices. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Introduce driver support for the MSI performance monitoring unit. The driver enables discovery and registration of PMU capabilities in MSI devices. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Resolve the count error issue caused by acquiring event index error for DDR PMU drivers. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
When CONFIG_ARCH_PHYTIUM and CONFIG_ACPI are not set, but CONFIG_COMPILE_TEST is enabled, the pcie pmu driver fails to compile. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Tan Rui <tanrui2142@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
Modify the enable logic in PCIe Link PMU driver to properly set up time mode and start-stop mode. Signed-off-by: Zhang Fuxiang <zhangfuxiang2144@phytium.com.cn> Signed-off-by: Fu Boyi <fuboyi2150@phytium.com.cn> Signed-off-by: Wang Yinfeng <wangyinfeng@phytium.com.cn>
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Pull request overview
This PR updates the Phytium PMU controller support to a newer driver version, expanding PCIe PMU functionality (including v2.0 support) and adding new PMU drivers for PCIe Link and MSI monitoring, along with build/metadata updates.
Changes:
- Refactors/enhances
phytium_pcie_pmuto support additional hardware versions and expanded event sets. - Adds new PMU drivers: PCIe Link PMU and MSI PMU.
- Updates
Kconfig/MakefileandMAINTAINERSto integrate the new drivers.
Reviewed changes
Copilot reviewed 7 out of 7 changed files in this pull request and generated 13 comments.
Show a summary per file
| File | Description |
|---|---|
MAINTAINERS |
Adds the new Phytium perf driver source files to the Phytium maintainer file list. |
drivers/perf/phytium/phytium_pcie_pmu.c |
Major PCIe PMU update: versioning, v1/v2 handling, expanded events, new configuration logic, IRQ handling adjustments. |
drivers/perf/phytium/phytium_pcie_link_pmu.c |
New PCIe Link PMU driver exposing link/TLP/DLLP/buffer-related counters via perf/sysfs. |
drivers/perf/phytium/phytium_msi_pmu.c |
New MSI PMU driver with perf integration, reqid filtering/timer configuration, and IRQ overflow handling. |
drivers/perf/phytium/Makefile |
Builds the new PCIe Link PMU and MSI PMU objects under new Kconfig symbols. |
drivers/perf/phytium/Kconfig |
Adds Kconfig options for PCIe Link PMU and MSI PMU; restructures/extends DDR PMU config. |
Comments suppressed due to low confidence (1)
drivers/perf/phytium/phytium_pcie_pmu.c:1404
- phytium_pcie_pmu_event_add() applies set_event_config() (writes HW config) before checking whether the event can be allocated (phytium_pcie_pmu_mark_event). If mark_event returns -EAGAIN/-ENODEV, the function exits with hardware reconfigured, potentially disrupting existing events. Allocate/validate the event first, then program hardware (or roll back on failure).
hwc->state |= PERF_HES_STOPPED;
pcie_pmu->ops->get_event_config(event, pcie_pmu);
ret = pcie_pmu->ops->set_event_config(event, pcie_pmu);
if (ret < 0)
return ret;
idx = phytium_pcie_pmu_mark_event(event);
if (idx < 0)
return idx;
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| writel(thd0_val, pcie_pmu->base + PCIE_V2_PMU_TIME_RG_THD_0); | ||
| writel(thd1_val, pcie_pmu->base + PCIE_V2_PMU_TIME_RG_THD_1); | ||
| writel(thd1_val, pcie_pmu->base + PCIE_V2_PMU_TIME_RG_THD_2); |
| } | ||
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| if ((event->attr.config & 0x1F) > PHYTIUM_PCIE_MAX_COUNTERS) | ||
| if ((event->attr.config & PHYTIUM_PCIE_EVENTS_MAX_MASK) > pcie_pmu->cnts_num) |
| val = phytium_pcie_pmu_get_stop_state(pcie_pmu); | ||
| phytium_pcie_pmu_unmark_event(pcie_pmu, hwc->idx); | ||
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| pcie_pmu->ops->reset_event_config(pcie_pmu); |
| u32 val64, val32_l, val32_h; | ||
| u32 idx = get_eventid(event); | ||
| u32 counter_offset = pcie_link_counter_reg_offset[idx]; | ||
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| if (!EVENT_VALID(idx)) { | ||
| dev_err(pcie_link_pmu->dev, "Unsupported event index:%d!\n", idx); | ||
| return 0; | ||
| } | ||
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| if (idx >= BUFFER_USAGE_TYPE_0) { | ||
| val32_l = readl(pcie_link_pmu->base + counter_offset); | ||
| if (idx % 2 == 0) | ||
| val32_l = (val32_l & REG_BUFFER_CURR_USAGE_MASK) >> 8; | ||
| else | ||
| val32_l = val32_l & REG_BUFFER_PEAK_USAGE_MASK; | ||
| val64 = (u64)val32_l; | ||
| } else if (idx == TLP_WINDOW_TIME_RX_TYPE || idx == TLP_WINDOW_TIME_TX_TYPE) { | ||
| val32_l = readl(pcie_link_pmu->base + counter_offset); | ||
| val32_h = readl(pcie_link_pmu->base + counter_offset - 4); | ||
| val64 = (u64)val32_h << 32 | (u64)val32_l; | ||
| } else if (idx > TLP_WINDOW_TIME_TX_TYPE && idx <= TLP_RX_HEADER_TOTAL_TYPE) { | ||
| val32_l = readl(pcie_link_pmu->base + counter_offset); | ||
| val32_h = readl(pcie_link_pmu->base + counter_offset + 4); | ||
| val64 = (u64)val32_h << 32 | (u64)val32_l; |
| u32 counter_offset = pcie_link_counter_reg_offset[idx]; | ||
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| if (!EVENT_VALID(idx)) { | ||
| dev_err(pcie_link_pmu->dev, "Unsupported event index:%d!\n", idx); | ||
| return 0; | ||
| } | ||
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| return -EINVAL; | ||
| } | ||
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| if ((event->attr.config & PHYTIUM_MSI_PMU_EVENT_MASK) > PHYTIUM_MISC_MAX_COUNTERS) |
| event = misc_pmu->pmu_events.hw_events[idx]; | ||
| if (!EVENT_VALID(idx)) { | ||
| dev_err(misc_pmu->dev, "Unsupported event index:%d!\n", idx); | ||
| return 0; | ||
| } | ||
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| reqid[i] = (u32)(0xFFFF & (reqid_val >> record_mov_bits)); | ||
| cnt_mov_bits = i * 4; | ||
| reqcnt[i] = (u32)(0xF & (req_cnt >> cnt_mov_bits)); | ||
| dev_info(misc_pmu->dev, "reqid(%u),cnt=%u\n", reqid[i], reqcnt[i]); |
| int idx, event_type; | ||
| unsigned long dev_stop_mask, dev_mask; | ||
| unsigned long *used_mask = misc_pmu->pmu_events.used_mask; | ||
| u32 opt_val = 0; | ||
| int event_added = bitmap_weight(used_mask, PHYTIUM_MISC_MAX_COUNTERS); | ||
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| // 0:pcu 1:pxu 2:peu | ||
| now_state = phytium_msi_pmu_get_now_status(misc_pmu); | ||
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| if (!is_interrupt_state(now_state)) | ||
| return IRQ_NONE; | ||
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| if (!event_added) { | ||
| phytium_msi_pmu_clear_counters(misc_pmu, MISC_MSI_MON_OPT_MASK); | ||
| return IRQ_HANDLED; | ||
| } | ||
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| stop_state = phytium_msi_pmu_get_stop_status(misc_pmu); | ||
| if (stop_state & MISC_MSI_MON_COUNT_FULL_MASK) { | ||
| for_each_set_bit(idx, used_mask, PHYTIUM_MISC_MAX_COUNTERS) { | ||
| event = misc_pmu->pmu_events.hw_events[idx]; | ||
| if (!event) | ||
| continue; | ||
| event_type = phytium_msi_pmu_get_event_type(event); | ||
| dev_stop_mask = pcie_dev_msi_mon_stop_mask[event_type]; | ||
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| if (stop_state & dev_stop_mask & MISC_MSI_MON_COUNT_FULL_MASK) { | ||
| phytium_msi_pmu_event_update(event); | ||
| opt_val |= pcie_dev_msi_mon_opt_bits[event_type]; | ||
| set_bit(event_type, &dev_mask); | ||
| } | ||
| } |
| static void phytium_msi_pmu_unmark_event(struct perf_event *event) | ||
| { | ||
| struct phytium_msi_pmu *misc_pmu = to_phytium_msi_pmu(event->pmu); | ||
| int idx = (int)misc_pmu_get_event(event); | ||
| int event_type = phytium_msi_pmu_get_event_type(event); | ||
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| if (!EVENT_VALID(idx)) { | ||
| dev_err(misc_pmu->dev, "Unsupported event index:%d!\n", idx); | ||
| return; | ||
| } | ||
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| clear_bit(idx, misc_pmu->pmu_events.used_mask); | ||
| clear_bit(event_type, misc_pmu->pmu_events.dev_mask); | ||
| } |
This patches updates the support for phytium PMU controller driver.