Phase 1: establish Rev A hardware contract and PCB

[danielbrownjr]

Summary

This draft PR tracks Jump Jet Phase 1 hardware definition and first Rev A PCB implementation.

It is intentionally opened before the PCB is complete so schematic corrections, mechanical decisions, footprint work, component selections, layout rationale, and validation evidence can accumulate in one reviewable place.

This PR is NOT fabrication-ready and does NOT authorize heater or fan actuation.

The current production firmware remains cold-safe and heater-incapable.

Current Phase 1 status

Completed / established:

• Phase 0 cold-safe firmware foundation merged to main
• Rev A.4.1 schematic package reviewed as the authoritative current schematic baseline
• Phase 1 hardware source-of-truth register established
• CZ4060 standalone heater characterization recorded
• 24 V / 200 W / 8.33 A retained as conservative heater-path design basis
• approximately 189 W / 7.89 A sustained heater behavior measured
• ESP32-S3 Super Mini physically identified
• preliminary ESP32 module geometry measured
• direct castellated module mounting selected as the production direction
• native four-wire PWM/tach fan architecture selected
• Sanyo Denki 9GA0424P3J001 selected for prototype characterization only
• Q1, F2, and J2 candidate parts identified
• PCB design correctly established as the next implementation stage, not a missing artifact
• power architecture separated conceptually into +5V_SYS/GATE and isolated/source-selected +5V_MCU
• gate-drive default-OFF requirements clarified

Current important design directions

Heater path

Current Rev A.4.1 topology:

+24V_PROT
-> F2
-> TF1
-> TS1
-> J2
-> external CZ4060 heater
-> Q1
-> GND

The heater path is sized using the conservative 8.33 A basis until full production-intent validation proves otherwise.

ESP32-S3 mounting

Current physical measurements:

• module PCB body: 23.67 × 17.91 mm
• overall length including USB-C: 25.07 mm
• USB-C overhang: approximately 1.40 mm
• 18 castellations
• nine per side
• nominal 2.54 mm pitch
• nominal 15.24 mm row spacing
• nominal 20.32 mm first-to-last pin-center span

Production direction:

• direct castellated soldering
• SMD carrier-board receiving lands
• central PCB window under the module for underside clearance
• optional temporary locating holes for assembly
• mandatory 1:1 physical fit verification before footprint freeze

ESP32 power

Preferred architecture:

protected 24 V
-> onboard regulator
-> +5V_SYS/GATE
-> isolated or source-selected +5V_MCU
-> ESP32-S3 Super Mini

USB-C is retained for:

• service
• flashing
• recovery
• debug

USB-C is not intended as the normal installed power source.

Mixed-source and backfeed behavior must be physically verified before freeze.

Fan architecture

The original Rev A.4.1 two-wire low-side-switched fan block is obsolete for the intended replacement fan.

Current direction:

• continuous fused 24 V fan power
• continuous ground
• separate open-drain PWM interface
• separate tach input
• configurable controller connection until GPIOs are frozen
• no RPM/stall thresholds until electrical and airflow characterization is complete

Gate drive

Rev A.4.1 currently uses SN74AHCT125 buffering with used OE inputs tied low.

Required correction:

• hardware-default-disabled heater gate drive
• gate-drive circuitry powered only from the 24 V-derived system rail
• USB-only MCU power must not energize Q1 drive
• retain direct Q1 gate pull-down
• qualify partial-power-down behavior
• add test points for gate-driver supply, OE, and Q1 gate

Current fabrication blockers

The first Rev A PCB must not be released for fabrication until the following are sufficiently closed:

• PCB envelope and mounting-hole definition
• connector-facing edges and USB datum
• castellation dimensions and exact registration
• physical pin numbering / Pin 1 verification
• underside component envelope and height
• PCB window and support-rail geometry
• antenna location and keepout
• USB shell / plug / service-access envelope
• temporary locating-header fit
• external 5 V / USB VBUS topology
• mixed-supply / backfeed behavior
• default-OFF gate-driver schematic correction
• complete regulator load and thermal analysis
• Q1 symbol/footprint multipad mapping
• F2 holder footprint verification
• TF1 / TS1 exact parts and mounting architecture
• J1 / F1 / MOD1 selections and footprints
• production PSU current-limit / fuse coordination
• final 1:1 ESP32 footprint fit check
• KiCad ERC / DRC on the production-intent design

Phase 1 review checklist

Mechanical / footprint

• Freeze PCB envelope and mounting holes
• Freeze connector-facing edges
• Verify ESP32 castellation dimensions
• Verify ESP32 pin numbering and Pin 1
• Measure underside component envelope and height
• Define ESP32 PCB window and support rails
• Define antenna keepout
• Define USB-C mechanical/access keepout
• Fit-test temporary locating header
• Generate production ESP32 footprint
• Pass 1:1 physical fit check

Power / protection

• Verify external 5 V / USB VBUS topology
• Define reverse-current/source-selection architecture
• Select and qualify 24 V -> 5 V regulator
• Complete 5 V load inventory
• Verify regulator chamber-temperature derating
• Correct gate-driver default-OFF behavior
• Verify partial-power-down behavior
• Add power-domain/OE/gate test points
• Coordinate fuse behavior against production PSU limits

Heater path

• Verify Q1 package/symbol/footprint mapping
• Verify Q1 thermal implementation
• Verify F2 holder footprint
• Select TF1 physical implementation
• Select TS1 physical implementation
• Confirm J2 production implementation
• Review all heater-path copper bottlenecks
• Review high-current return geometry

Fan

• Replace obsolete two-wire fan schematic block
• Implement continuous fused 24 V fan power
• Implement open-drain PWM interface
• Implement protected tach input
• Characterize PWM electrical behavior
• Characterize tach pulse behavior
• Characterize startup / minimum reliable speed
• Characterize RPM vs duty
• Characterize stall / locked-rotor behavior
• Characterize installed airflow and hub temperature
• Derive RPM/stall thresholds from evidence

PCB

• Create first Rev A .kicad_pcb
• Place high-current / safety path first
• Review copper widths and neckdowns
• Review Q1 thermal spreading
• Review fuse-holder and connector pad heating
• Review ground / return strategy
• Review thermistor ADC noise exposure
• Review antenna clearance
• Run KiCad ERC / DRC
• Review 3D/mechanical fit
• Complete fabrication-readiness review

Safety boundary

Nothing in this PR should be interpreted as authorization for heater actuation.

Firmware remains cold-safe until the hardware path, sensing, fan proof, safety interlocks, and physical protections are implemented and validated.

Firmware does not replace:

• fusing
• independent thermal cutoff
• correctly rated wiring/connectors
• MOSFET derating
• PCB copper/clearance requirements
• airflow validation
• temperature-suitable materials

Source of truth

Primary Phase 1 tracking documents:

• ROADMAP.md
• TODO.md
• docs/HARDWARE_BASELINE.md
• docs/PHASE1_HARDWARE_REGISTER.md
• docs/PRODUCT_SAFETY_CONTRACT.md

The hardware register is the living record of confirmed facts, measurements, design decisions, candidates, assumptions, and blockers.

Merge criteria

Do not merge this PR merely because the first PCB exists.

Phase 1 should only be considered merge-ready after:

• the Rev A hardware contract is reviewed
• critical component and footprint mappings are resolved
• first PCB is created and reviewed
• safety-critical schematic corrections are complete
• fabrication blockers are either closed or explicitly accepted with evidence
• documentation is synchronized
• no candidate is silently promoted to BOM-final
• no firmware GPIO/ADC/PWM/RPM/thermal constants are frozen without supporting hardware evidence