chore: release v0.5.0

[github-actions]

🤖 New release

• thevenin-types: 0.3.0 -> 0.5.0
• thevenin-xspice: 0.1.2 -> 0.5.0
• cirq-ast: 0.1.0 -> 0.5.0
• cirq-grammar: 0.1.0 -> 0.5.0
• cirq-control-grammar: 0.1.0 -> 0.5.0
• cirq-ir: 0.1.0 -> 0.5.0
• cirq-frontend: 0.1.0 -> 0.5.0
• thevenin: 0.3.0 -> 0.5.0
• cirq-spice-import: 0.1.0 -> 0.5.0
• thevenin-control: 0.1.0 -> 0.5.0
• thevenin-test-macro: 0.1.1 -> 0.5.0
• thevenin-cirq: 0.1.0 -> 0.5.0

Changelog

thevenin-types

0.5.0 - 2026-07-12

Added

• update ngspice submodule (1a621eb -> 037b657), pass its new convergence test
• complete Goal C — SPICE importer accepts arbitrary netlists
• (urc) SPICE U element + URC model with importer-side expansion
• (fourier) .four (DFT harmonics + THD) and .fft (windowed FFT) post-processing of .tran
• (tline) add T element (ideal lossless transmission line)
• (importer) MOS3 warning, line continuation, .step diagnostic, TEMPER + ternary in brace eval
• (switches) add S/W voltage- and current-controlled switches
• (importer) R/L/C tc=, option scale, .width, graceful unknown directives
• (csparam) support .csparam directive with control-scope seeding
• close remaining SPICE import gaps — nodeset, measure, multi-temp, arithmetic expressions

Fixed

• un-ignore hfet/inverter with corrected reference from patched ngspice

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• (thevenin) neutral ModelParams boundary, Expr-free device layer
• polish docs.rs landing pages, examples, and metadata

thevenin-xspice

0.5.0 - 2026-07-12

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• polish docs.rs landing pages, examples, and metadata

cirq-ast

0.5.0 - 2026-07-12

Added

• (cirq) complete Goal B — language registry, native URC, port arrays
• (cirq) compile-time if/elseif/else conditionals
• (cirq) native measure expression syntax (= expr form)
• (cirq) ternary operator + sim-context constants (temper, time, freq, hertz)
• (cirq) native measure block syntax
• add export blocks and named imports to Cirq language

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• polish docs.rs landing pages, examples, and metadata

cirq-grammar

0.5.0 - 2026-07-12

Added

• (cirq) complete Goal B — language registry, native URC, port arrays
• (cirq) compile-time if/elseif/else conditionals
• (cirq) native measure expression syntax (= expr form)
• (grammar) tree-sitter-control + scanner finishes bash/js/control 1.0
• (cirq) ternary operator + sim-context constants (temper, time, freq, hertz)
• (cirq-grammar) inject embedded languages in code blocks
• (cirq) native measure block syntax
• add export blocks and named imports to Cirq language

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• polish docs.rs landing pages, examples, and metadata
• (cirq-grammar) scaffold multi-language tree-sitter bindings

cirq-control-grammar

0.5.0 - 2026-07-12

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• polish docs.rs landing pages, examples, and metadata

cirq-ir

0.5.0 - 2026-07-12

Added

• complete Goal C — SPICE importer accepts arbitrary netlists
• (cirq) complete Goal B — language registry, native URC, port arrays
• (cirq) native measure expression syntax (= expr form)
• (grammar) tree-sitter-control + scanner finishes bash/js/control 1.0
• (control) source command, measure command, vector arithmetic in print
• (meas) ERR/ERR1/ERR2/ERR3 + IF conditional + FILE= output
• (fourier) .four (DFT harmonics + THD) and .fft (windowed FFT) post-processing of .tran
• (vdmos) port vertical-DMOS power MOSFET from ngspice
• (output) ngspice raw file format (binary + ASCII) + CSV + write command
• (tline) add T element (ideal lossless transmission line)
• (switches) add S/W voltage- and current-controlled switches
• (control) add while, repeat, save commands
• (csparam) support .csparam directive with control-scope seeding
• (control) typed control AST in IR; executor consumes parsed form
• (meas) typed MeasureExpr in IR, add PARAM=/LAST/TD support
• (mna) sens Netlist-free; multi-temp on Circuit; SimContext Netlist private
• route ngspice harness through Cirq IR via THEVENIN_VIA_CIRQ
• close remaining SPICE import gaps — nodeset, measure, multi-temp, arithmetic expressions

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• native ModelParams::from_ir, drop convert_model on Circuit device loads
• polish docs.rs landing pages, examples, and metadata
• (release) README pass, CHANGELOG, api-stability + #[non_exhaustive] on public enums

cirq-frontend

0.5.0 - 2026-07-12

Added

• (cirq) complete Goal B — language registry, native URC, port arrays
• (cirq) native four / fft analysis blocks
• (cirq) compile-time if/elseif/else conditionals
• (cirq) native measure expression syntax (= expr form)
• (cirq) ternary operator + sim-context constants (temper, time, freq, hertz)
• (fourier) .four (DFT harmonics + THD) and .fft (windowed FFT) post-processing of .tran
• (vdmos) port vertical-DMOS power MOSFET from ngspice
• (tline) add T element (ideal lossless transmission line)
• (switches) add S/W voltage- and current-controlled switches
• (cirq) native measure block syntax
• (control) typed control AST in IR; executor consumes parsed form
• (meas) typed MeasureExpr in IR, add PARAM=/LAST/TD support
• (cirq-frontend) module parameter overrides at instantiation
• (control) retire SimContext::netlist cache; dispatch .control via Circuit
• (cirq-frontend) netlist_analysis_to_ir converter
• delete --legacy CLI flag and deprecated Netlist control entry points
• (mna) sens Netlist-free; multi-temp on Circuit; SimContext Netlist private
• (mna) direct IR -> MNA path supports diodes
• (mna) assemble MnaSystem directly from Cirq IR (linear subset)
• support BSIM4 model binning through Cirq IR round-trip
• route ngspice harness through Cirq IR via THEVENIN_VIA_CIRQ
• wire .ic/UIC, .nodeset, .meas, multi-temp, and mutual coupling
• close remaining SPICE import gaps — nodeset, measure, multi-temp, arithmetic expressions
• resolve SPICE parametric expressions and sanitize numeric node names
• add export blocks and named imports to Cirq language

Fixed

• guard two stack-overflow DoS paths reachable from untrusted input
• populate netlist.source on Cirq IR -> Netlist round-trip
• restore Expr::Brace on Cirq IR -> Netlist round-trip

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• native ModelParams::from_ir, drop convert_model on Circuit device loads
• polish docs.rs landing pages, examples, and metadata
• (control) parse .control analyses straight to IR
• (release) README pass, CHANGELOG, api-stability + #[non_exhaustive] on public enums
• Merge doc archival
• archive cirq-plan and migration plans
• demote Netlist-shaped simulator APIs to pub(crate)
• (mna) add MNA-on-IR pivot plan; promote to_netlist shims to pub
• (control) deprecate Netlist-shaped .control entry points (Stage 4 / Phase D)

thevenin

0.5.0 - 2026-07-12

Added

• update ngspice submodule (1a621eb -> 037b657), pass its new convergence test
• (hisim) faithful HiSIM2 I-V core (Phases 2+3), un-ignore golden tests
• (hisim) faithful HiSIM2 constants + full-port plan (Phase 1)
• add GSHUNT option, complete the .options survey
• complete Goal C — SPICE importer accepts arbitrary netlists
• (cirq) native measure expression syntax (= expr form)
• (expr) short-circuit ternary cond ? then : else
• (cirq) ternary operator + sim-context constants (temper, time, freq, hertz)
• (control) source command, measure command, vector arithmetic in print
• (options) DEFAD/DEFAS/DEFL/DEFW + NOOPALTER + GMINPRIORITY
• (numerics) iterative refinement, TRTOL, PIVTOL/PIVREL
• (meas) ERR/ERR1/ERR2/ERR3 + IF conditional + FILE= output
• (transient) .options METHOD=trap|gear|euler with BDF2 for L/C
• (urc) SPICE U element + URC model with importer-side expansion
• (hisim) port HiSIM2 (LEVEL=68) surface-potential MOSFET (partial)
• (bsim2) port BSIM2 MOSFET (level 5) from ngspice - initial build
• (bsim1) port BSIM1 MOSFET (level 4) from ngspice
• (fourier) .four (DFT harmonics + THD) and .fft (windowed FFT) post-processing of .tran
• (vdmos) port vertical-DMOS power MOSFET from ngspice
• (mos3) port MOSFET Level 3 (semi-empirical short-channel) from ngspice
• (output) ngspice raw file format (binary + ASCII) + CSV + write command
• (tline) add T element (ideal lossless transmission line)
• (sens) AC sensitivity analysis (.sens v(...) ac ...) — tests and verification
• (options) RSHUNT, GMINSTEPS, NOOPITER
• (importer) MOS3 warning, line continuation, .step diagnostic, TEMPER + ternary in brace eval
• (switches) add S/W voltage- and current-controlled switches
• (importer) R/L/C tc=, option scale, .width, graceful unknown directives
• (meas) typed MeasureExpr in IR, add PARAM=/LAST/TD support
• (control) retire SimContext::netlist cache; dispatch .control via Circuit
• (control) implement stop/resume + unignore resume-1.cir (101/0/6)
• (mna) sens Netlist-free; multi-temp on Circuit; SimContext Netlist private
• (mna) add Circuit-input top-level simulate dispatcher; CLI uses it
• (mna) TF / PZ / Noise also fully Netlist-free on Circuit-input path
• (mna) add Circuit-input entry points for tf/pz/noise/sens
• (mna) transient analysis fully Netlist-free on Circuit-input path
• (mna) DC and AC analyses fully Netlist-free on Circuit-input path
• (mna) route harness through mna_ir; complete _with_mna surface
• (mna) route DC/AC/TRAN through mna_ir on Circuit-input path
• (mna) direct IR -> MNA path supports LTRA/TXL/CPL/XSPICE (full coverage)
• (mna) direct IR -> MNA path supports BehavioralSource + Coupling
• (mna) direct IR -> MNA path supports JFET / MESA family
• (mna) direct IR -> MNA path supports MOSFET family
• (mna) direct IR -> MNA path supports BJT (level 1 + VBIC)
• (mna) direct IR -> MNA path supports diodes
• (mna) share OP solve+format between Netlist and IR direct paths
• (mna) assemble MnaSystem directly from Cirq IR (linear subset)
• (control) add IR-shaped .control entry point (Stage 4 / Phase A)
• (circuit) extend direct IR -> MNA path to dependent sources
• (circuit) land direct IR -> MNA path for linear-only DC OP
• graduate Circuit-input simulation API into thevenin
• support BSIM4 model binning through Cirq IR round-trip
• make Cirq IR the default harness route, quarantine 5 round-trip failures
• route ngspice harness through Cirq IR via THEVENIN_VIA_CIRQ
• wire .ic/UIC, .nodeset, .meas, multi-temp, and mutual coupling

Fixed

• guard two stack-overflow DoS paths reachable from untrusted input
• (bjt) remove double-counted substrate cap, un-ignore rtlinv — 0 ignored tests
• PULSE PER defaults to TSTOP; BJT substrate cap + absolute charge integration
• (bsim3soidd) honor debug=-1 quasi-static semantics, un-ignore RampVg2
• (bjt) use ngspice's CONSTKoverQ thermal voltage, not legacy SPICE3 KboQ
• (bsim3soidd) numerically stable Phi^1.5/Phi^2.5 differences in CAPMOD=3
• un-ignore hfet/inverter with corrected reference from patched ngspice
• (bsim3soidd) re-resolve XJ sentinel against the model card's TSI
• (bsim1) default NRD/NRS to 1 per ngspice b1set.c, un-ignore bsim1 harness fixture
• (raw_output) explicit plotnames for .four/.fft/.disto; flag unknown
• (fourier) ngspice 200-sample DFT grid, window gain, narrower visibility
• (transient) only count bootstrap-driven BE steps toward Gear budget
• (hisim) drop CLM unit double-conversion; demote checklist to partial
• (vdmos) use raw signed vds in lambda factor
• (bsim1) unconditional dvth_dvbs across Vbs=0 seam
• (mna_ir) repair merge artefact in nr_options_from_circuit boolean dispatch
• (hisim) residual-based convergence + flag in solve_surface_potential
• (bsim2) repair bad rebase merge of bsim1/bsim2 dispatch blocks
• (bsim3soi-dd) correct DELTA_VCSCV from 1e-5 to 4e-4 to match ngspice
• populate netlist.source on Cirq IR -> Netlist round-trip
• restore Expr::Brace on Cirq IR -> Netlist round-trip
• add RHS history coupling for mutual inductors in transient

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• un-ignore schmitt with bounded-error tolerance; add harness profile mode
• refresh HiSIM dispatch comments for the faithful port
• un-ignore bsim2 harness fixture, now passing against ngspice reference
• (hisim) add HiSIM2 golden-reference scaffold (Phase 0)
• IR-native source DC + waveforms, drop convert_source_spec from the simulator
• make mna_ir device loading IR-native, drop convert_model/extra_params
• [breaking] remove the legacy Netlist stamping path
• route in-crate unit tests through the IR path via test_support
• native ModelParams::from_ir, drop convert_model on Circuit device loads
• (thevenin) neutral ModelParams boundary, Expr-free device layer
• rustdoc polish, README refresh, getting-started guide
• polish docs.rs landing pages, examples, and metadata
• (thevenin) demote assemble_mna(&Netlist) to pub(crate)
• (thevenin) mark CircuitSimError #[non_exhaustive]
• (release) README pass, CHANGELOG, api-stability + #[non_exhaustive] on public enums
• (bsim2) set vbb=-3 in integration test model for proper body effect
• (bsim2) rustfmt single-line mos_limit calls
• (bsim2) adjust cutoff threshold for subthreshold conduction
• (bsim2) apply rustfmt + extend ignore.toml note for bsim2/test.cir
• (bsim2) add integration tests + update docs
• (switch,fourier) correct stale documentation
• (fourier) satisfy clippy neg_cmp_op_on_partial_ord + useless_format
• (fourier) relax pure-sine unit-test tolerances for interpolation leakage
• Merge importer hygiene (R tc=, option scale, .width, unknown directives)
• Merge doc archival
• archive cirq-plan and migration plans
• (xspice) add Circuit-input simulate_op_with_xspice, retire Netlist wrapper
• demote Netlist-shaped simulator APIs to pub(crate)
• (stamp) extend companion bypass to MOS6 (Level 6)
• (stamp) record why BJT companion bypass isn't enabled
• (stamp) companion bypass for Level 1 + Level 2 MOSFETs (ngspice CKTbypass)
• (ac) hoist omega-independent stamps into AcStampCache; bench complex solves
• (sparse) reuse symbolic LU across NR iterations and timesteps
• (bsim3soi-dd) refine RampVg2 diagnosis after chain audit
• (soi-dd) correct RampVg2 diagnosis — physics, not convergence
• add AC analysis test for coupled inductors

cirq-spice-import

0.5.0 - 2026-07-12

Added

• complete Goal C — SPICE importer accepts arbitrary netlists
• (cirq) complete Goal B — language registry, native URC, port arrays
• (expr) short-circuit ternary cond ? then : else
• (urc) SPICE U element + URC model with importer-side expansion
• (fourier) .four (DFT harmonics + THD) and .fft (windowed FFT) post-processing of .tran
• (vdmos) port vertical-DMOS power MOSFET from ngspice
• (tline) add T element (ideal lossless transmission line)
• (importer) resolve .include and .lib file I/O with search path, cycle detection, and Latin-1 fallback
• (importer) MOS3 warning, line continuation, .step diagnostic, TEMPER + ternary in brace eval
• (switches) add S/W voltage- and current-controlled switches
• (importer) R/L/C tc=, option scale, .width, graceful unknown directives
• (csparam) support .csparam directive with control-scope seeding
• (control) typed control AST in IR; executor consumes parsed form
• (meas) typed MeasureExpr in IR, add PARAM=/LAST/TD support
• (mna) sens Netlist-free; multi-temp on Circuit; SimContext Netlist private
• support BSIM4 model binning through Cirq IR round-trip
• route ngspice harness through Cirq IR via THEVENIN_VIA_CIRQ
• close remaining SPICE import gaps — nodeset, measure, multi-temp, arithmetic expressions
• resolve SPICE parametric expressions and sanitize numeric node names

Fixed

• (urc) use urc sigil for synthetic nodes to avoid user collision

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• polish docs.rs landing pages, examples, and metadata
• (release) README pass, CHANGELOG, api-stability + #[non_exhaustive] on public enums
• Merge csparam support
• demote Netlist-shaped simulator APIs to pub(crate)

thevenin-control

0.5.0 - 2026-07-12

Added

• update ngspice submodule (1a621eb -> 037b657), pass its new convergence test
• complete Goal C — SPICE importer accepts arbitrary netlists
• (cirq) complete Goal B — language registry, native URC, port arrays
• (control) source command, measure command, vector arithmetic in print
• (fourier) .four (DFT harmonics + THD) and .fft (windowed FFT) post-processing of .tran
• (output) ngspice raw file format (binary + ASCII) + CSV + write command
• (control) add while, repeat, save commands
• (csparam) support .csparam directive with control-scope seeding
• (control) typed control AST in IR; executor consumes parsed form
• (control) retire SimContext::netlist cache; dispatch .control via Circuit
• (control) implement stop/resume + unignore resume-1.cir (101/0/6)
• delete --legacy CLI flag and deprecated Netlist control entry points
• (mna) sens Netlist-free; multi-temp on Circuit; SimContext Netlist private
• (control) alter mutates Circuit.elements / Circuit.models (Stage 4 / Phase C)
• (control) SimContext owns the driving Circuit (Stage 4 / Phase B)
• (control) add IR-shaped .control entry point (Stage 4 / Phase A)

Fixed

• .control 'run' now executes netlist's declared analysis

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• rustdoc polish, README refresh, getting-started guide
• polish docs.rs landing pages, examples, and metadata
• (control) parse .control analyses straight to IR
• (release) README pass, CHANGELOG, api-stability + #[non_exhaustive] on public enums
• Merge .control while/repeat/save commands
• (control) @device[param] lookup walks Circuit instead of cached Netlist
• (control) deprecate Netlist-shaped .control entry points (Stage 4 / Phase D)

thevenin-test-macro

0.5.0 - 2026-07-12

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• update facet to 0.46 and refresh all deps

thevenin-cirq

0.5.0 - 2026-07-12

Added

• (cirq) native four / fft analysis blocks
• (cirq) native measure expression syntax (= expr form)
• (control) retire SimContext::netlist cache; dispatch .control via Circuit
• (mna) sens Netlist-free; multi-temp on Circuit; SimContext Netlist private
• (mna) add Circuit-input top-level simulate dispatcher; CLI uses it
• (mna) route DC/AC/TRAN through mna_ir on Circuit-input path
• (mna) direct IR -> MNA path supports LTRA/TXL/CPL/XSPICE (full coverage)
• (mna) direct IR -> MNA path supports BehavioralSource + Coupling
• (mna) direct IR -> MNA path supports JFET / MESA family
• (mna) direct IR -> MNA path supports MOSFET family
• (mna) direct IR -> MNA path supports BJT (level 1 + VBIC)
• (mna) direct IR -> MNA path supports diodes
• (mna) assemble MnaSystem directly from Cirq IR (linear subset)
• (circuit) extend direct IR -> MNA path to dependent sources
• graduate Circuit-input simulation API into thevenin
• (thevenin-cirq) add SPICE-source convenience entry points
• add thevenin-cirq crate as Stage 4 simulation surface
• scaffold Cirq language, grammar, IR crates, and spec
• (cli) add SPICE-to-CirQ converter command
• (control) implement .control block interpreter

Fixed

• (cirq) harden CirQ parser, fix spec divergence, add digital domain inference

Other

• (release) unify workspace to 0.5.0 for first crates.io release
• polish docs.rs landing pages, examples, and metadata
• demote Netlist-shaped simulator APIs to pub(crate)
• tighten tolerance overrides for 5 harness tests
• fork netlists at analysis boundaries — one Netlist per analysis
• replace serde with facet for deserialization

---

This PR was generated with release-plz.