Home

Welcome to the CIX Linux Kernel Upstream wiki!

This wiki page is used for CIX SoCs mainline Linux kernel status update.

Upstream Status

CIX P1 (Sky1) SoC
Component	Status	Link
Basic DT	v6.17-rc1	https://lore.kernel.org/all/20250721144500.302202-1-peter.chen@cixtech.com/
MAILBOX/UART/Clock	v6.17-rc1	https://lore.kernel.org/all/20250721144500.302202-1-peter.chen@cixtech.com/
I2C & I3C	v6.18-rc1	https://lore.kernel.org/all/20250903084713.3221907-1-jun.guo@cixtech.com/
SPI	v6.19-rc1	https://lore.kernel.org/r/20250919013118.853078-1-jun.guo@cixtech.com/
Pinctrl	v6.19-rc1	https://lore.kernel.org/all/20251021070410.3585997-1-gary.yang@cixtech.com/
PCIe	v6.19-rc1	https://lore.kernel.org/linux-pci/20251020042857.706786-1-hans.zhang@cixtech.com/
HDA	v6.19-rc1	v6
Reset	v7.1-rc1	v3
DMA	Reviewing	https://lkml.org/lkml/2025/11/17/69
GPIO	v7.1-rc1	https://lore.kernel.org/r/20260312094923.3473444-2-zichar.zhang@cixtech.com
Power Domain	v7.1-rc1	https://lore.kernel.org/all/20260313114914.1564115-1-gary.yang@cixtech.com/
USB	Reviewing	https://lore.kernel.org/r/20260421023459.506145-3-peter.chen@cixtech.com
DPU	v7.1-rc1	https://lore.kernel.org/all/20260313033119.33686-1-cunyuan.liu@cixtech.com/
USB3 PHY	Planning
USB/DP Combo PHY	Planning
CPU Idle	v7.2-rc1	https://lore.kernel.org/r/20260424043436.162009-1-Devin.Li@cixtech.com
CPU DVFS	v7.2-rc1	https://lore.kernel.org/r/20260506025254.3602623-1-Devin.Li@cixtech.com
I2S	Planning
DP	Planning
GPU	Planning
VPU	Won't do
CSI	Won't do
RPMSG	Won't do
GMAC	Won't do
System PM	Won't do
CIX P1 (Sky1) SoC based boards
Component	Status	Link
Radxa Orion O6	v6.17-rc1	https://lore.kernel.org/all/20250721144500.302202-1-peter.chen@cixtech.com/
Xunlong Orangepi 6 plus	v7.0-rc1	v4