Catalyst N2

Open source neuromorphic processor. Compartmental LIF neurons, microcode learning with eligibility traces, synaptic delays, sync/async NoC, RISC-V management. Verilog RTL, validated on AWS F2 and Kria K26.

Second generation of Catalyst N1. Same scalable architecture, significantly more capable core.

What changed from N1

The core pipeline is the main difference. N1 has a basic LIF neuron with a 14-opcode learning engine. N2 adds compartmental dendrites, graded spike transmission, programmable synaptic delays, a 64-instruction microcode engine with eligibility traces for three-factor learning, noise injection, skip-idle optimization, and an async NoC option. Memory layout, multi-chip, RISC-V cluster, and host interface are structurally the same.

Specifications

Parameter	Value
Neuron model	LIF with 4 dendritic compartments (16-bit fixed-point)
Graded spikes	Variable magnitude transmission
Synaptic delays	0-63 timesteps per connection (6-bit)
Learning	64-instruction microcode, 8-register file, STDP + three-factor
Eligibility traces	Reward-modulated, exponential decay
Noise	LFSR stochastic injection per core
Network-on-Chip	Barrier-synchronized mesh or async event-driven (selectable)
Host interface	UART (FPGA) / AXI-Lite (F2)
Management	Triple RV32I cluster with debug
Multi-chip	Serial links, 14-bit addressing (up to 16K chips)
Clock	62.5 MHz (F2), 100 MHz (Kria)

FPGA configurations

Target	Device	Cores	Neurons/core	Total neurons	Clock
AWS F2	VU47P	16	1,024	16,384	62.5 MHz
Kria KV260	ZU5EV	2	256	512	100 MHz
Arty A7	XC7A100T	4	256	1,024	100 MHz

Full 128-core config needs ~150 MB SRAM, so validated at reduced core counts. BRAM is the binding constraint.

Per-core memory

Memory	Entries	Width	KB
Connection pool (weight)	131,072	16b	256
Connection pool (target)	131,072	10b	160
Connection pool (delay)	131,072	6b	96
Connection pool (tag)	131,072	16b	256
Eligibility traces	131,072	16b	256
Reverse connection table	32,768	28b	112
Index table	1,024	41b	5.1
Other (state, traces, microcode, delay ring)	~20K	var	~60
Total per core			~1.2 MB

Learning engine registers

Register	Name	Description
R0	TRACE1	Pre-synaptic trace
R1	TRACE2	Post-synaptic trace
R2	WEIGHT	Connection weight
R3	ELIG	Eligibility trace
R4	CONST	Loaded constant
R5	TEMP0	Temporary
R6	TEMP1	Temporary
R7	REWARD	Reward signal

Opcodes: ADD, SUB, MUL, SHR, SHL, MAX, MIN, LOADI, STORE_W, STORE_E, SKIP_Z, SKIP_NZ, HALT, NOP.

Directory structure

catalyst-n2/
  rtl/           16 Verilog modules
  tb/            39 testbenches
  sdk/           Python SDK (CPU, GPU, UART, PCIe backends)
  fpga/          Build files for Arty A7, AWS F2, Kria KV260
  formal/        Formal verification (SRAM, FIFO)
  Makefile       Compile and run simulation

Simulation

Requires Icarus Verilog (v12+).

make sim

# Full regression
bash run_n2_regression.sh

# Single testbench
iverilog -g2012 -DSIMULATION -o out.vvp rtl/*.v tb/tb_p25_final.v
vvp out.vvp

SDK

cd sdk
pip install -e .

import neurocore as nc

net = nc.Network()
inp = net.population(100, params={'threshold': 1000, 'leak': 10})
out = net.population(10, params={'threshold': 1000, 'leak': 5})
net.connect(inp, out, weight=500, p=0.3)

sim = nc.Simulator()
sim.deploy(net)
sim.inject(inp, current=1500)
result = sim.run(100)
result.raster_plot(show=True)

Custom learning rules via microcode:

from neurocore import LearningRule, OP_SUB, OP_MUL, OP_STORE_W, OP_HALT
from neurocore import R_TRACE1, R_TRACE2, R_WEIGHT, R_TEMP0

rule = LearningRule()
rule.add(OP_SUB, R_TEMP0, R_TRACE1, R_TRACE2)
rule.add(OP_MUL, R_TEMP0, R_TEMP0, R_WEIGHT)
rule.add(OP_STORE_W, 0, R_TEMP0, 0)
rule.add(OP_HALT, 0, 0, 0)

Four backends: Simulator (CPU), GpuSimulator (PyTorch CUDA), Chip (UART), F2 (PCIe). Same API for all.

FPGA

Arty A7

vivado -mode batch -source fpga/build_vivado.tcl

AWS F2

cd fpga/f2
bash run_build.sh

CL wrapper: fpga/f2/cl_neuromorphic.sv. Host driver: fpga/f2_host.py.

Kria KV260

vivado -mode batch -source fpga/kria/run_impl.tcl

Benchmarks

cd sdk
python benchmarks/shd_train.py --data-dir benchmarks/data/shd --epochs 200
python benchmarks/shd_deploy.py --checkpoint benchmarks/shd_model.pt --data-dir benchmarks/data/shd

Additional benchmarks: DVS gesture recognition, XOR classification, temporal patterns, noise-driven exploration, GPU scaling, stress tests.

Links

• Catalyst N1 (first generation)
• catalyst-neuromorphic.com

License

Apache 2.0. See LICENSE.