FPGA & RTL Design Engineer | Embedded Systems | Digital Verification | Former Navy Nuclear Electronics Technician

I am a Computer Engineering student at UConn with prior experience as a Navy Nuclear Electronics Technician and Reactor Operator on USS South Dakota (SSN-790).

My work is centered on FPGA design, RTL implementation, embedded systems, and verification. I am especially interested in systems that need to be predictable under real operating constraints, whether that means timing closure, testbench quality, hardware-software interfaces, or fault handling.

My background in naval nuclear operations shaped how I approach engineering work. I value clear requirements, disciplined execution, traceability, and designs that can be understood and verified by other people.

• Languages: VHDL, Verilog, SystemVerilog
• Tools: Vivado, GHDL, LogicWorks, Xilinx IP Catalog
• Experience with synthesis, place and route, timing analysis, and debug
• Design areas include finite state machines, datapaths, pipelining, CDC considerations, and peripheral integration
• Familiar with board-level interfaces including SPI, I²C, ADC/DAC integration, and memory-mapped control paths

• SystemVerilog testbench development
• Assertion-based verification and coverage-oriented workflows
• Directed and constrained-random testing
• Comfortable building monitors, scoreboards, checkers, and regression-oriented test structure
• Familiar with linting, simulation, and validation workflows used in digital design environments

• Languages: C, C++, Python, MATLAB, Haskell
• Platforms: AVR, ARM Cortex-M, ESP32, RISC-V
• Experience with bare-metal programming, interrupt-driven systems, and real-time task structure
• Protocols: UART, SPI, I²C, CAN, JTAG
• Interested in firmware that interacts closely with hardware and supports deterministic system behavior

• Translating design intent into workable RTL and interface logic
• Working across hardware, firmware, simulation, and lab validation
• Tradeoff analysis across timing, complexity, maintainability, and implementation cost
• Strong preference for designs that are testable, reviewable, and easy to reason about

Jun 2025 – Aug 2025

• Worked on FPGA-DSP interface development for naval defense systems
• Supported integration between Microchip IGLOO2 SoC FPGAs and Texas Instruments DSP processors
• Built MATLAB control-loop simulations for electromechanical modeling
• Implemented memory-mapped control interfaces tied to hardware error-detection logic
• Assisted with integration, debug, and failure analysis in a mission-critical electronics environment

Aug 2024 – Dec 2025

• Developed MATLAB and Python workflows for ECG R-peak detection, HRV analysis, and biosignal synchronization
• Processed and validated multimodal wearable sensor data including ECG, EDA, PPG, and respiration
• Contributed to peer-reviewed research involving signal-processing methodology
• Built repeatable data-processing pipelines for research and validation use

Mar 2017 – Jul 2023

• Operated and maintained reactor instrumentation, control, and support systems across normal and casualty conditions
• Performed maintenance and troubleshooting on mission-critical electronics and control systems
• Worked from procedures, technical documentation, schematics, and test data to diagnose and repair faults
• Led maintenance evolutions and supervised high-consequence work under strict procedural controls
• Mentored junior technicians and operators in both maintenance and operations
• Qualifications included Propulsion Plant Operator, Shutdown Reactor Operator, Submarine Reactor Controls, QA Craftsman, and Qualified Submarines

• Designed control-path and datapath components for a RISC-V processor
• Focused on control logic, pipeline behavior, and verification structure

• Built bare-metal and interrupt-driven microcontroller programs
• Worked at the register level with timing-sensitive control logic

• Implemented producer-consumer patterns and bounded-buffer coordination with POSIX threads
• Focused on synchronization correctness and predictable behavior under concurrency

• Used Haskell for recursive algorithms, higher-order functions, and type-safe program structure
• Useful for thinking clearly about data flow and transformation logic

University of Connecticut
B.S. in Computer Engineering
Expected Spring 2027
GPA: 3.986

Relevant Coursework
Digital Logic Design, Digital Systems Design, Computer Architecture, Systems Programming, Operating Systems, Microprocessor Applications Lab, Signals and Systems, Electronic Circuit Design, Numerical Methods, Linear Algebra, Differential Equations

Advanced Technical Training
U.S. Navy Nuclear Power School (2018)
Training in reactor physics, thermodynamics, electrical power systems, instrumentation and control, radiological controls, and propulsion plant operation

• Email: arturojsalinas@outlook.com
• Phone: +1-956-400-9965
• Location: Groton, CT

I do well in environments where the work is technical, the standards are high, and the output has to hold up under review. My strongest habits are careful execution, solid documentation, and staying close to how a system behaves in practice rather than how it looks on paper.